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[/] [System09/] [trunk/] [rtl/] [Spartan3/] [ram2k_b16.vhd] - Diff between revs 66 and 99

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--===========================================================================--
 
--                                                                           --
 
--            Synthesizable 2K RAM using Xilinx RAMB16_S9 Block RAM          --
 
--                                                                           --
 
--===========================================================================--
 
--
 
--  File name      : ram2k_b16.vhd
 
--
 
--  Entity name    : ram_2k
 
--
 
--  Purpose        : Implements 2KBytes of RAM using one Xilinx RAMB16_S9 Block RAM
 
--                   Essentially a wrapper for a 2KByte RAM block for different 
 
--                   technology FPGAs. Used in vdu8.vhd for the System09 SoC as a 
 
--                   character buffer and attribute RAM. Initiatized with rubbish 
 
--                   so that the VDU displays random characters on start up to
 
--                   indicate it is working correctly.
 
--
 
--  Dependencies   : ieee.std_logic_1164
 
--                   ieee.std_logic_arith
 
--
 
--  Uses           : RAMB16_S9 (Xilinx 16KBit Block RAM)
 
--
 
--  Author         : John E. Kent
 
--
 
--  Email          : dilbert57@opencores.org      
 
--
 
--  Web            : http://opencores.org/project,system09
 
--
 
--  Description    : Block RAM instatiation
 
--
 
--  Copyright (C) 2010 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================--
 
--                                                                           --
 
--                              Revision  History                            --
 
--                                                                           --
 
--===========================================================================--
 
--
 
-- Version Date        Author     Changes
 
--
 
-- 0.1     2010-06-17  John Kent  Added GPL and header
 
--
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
library unisim;
        use unisim.vcomponents.all;
        use unisim.vcomponents.all;
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entity ram_2k is
entity ram_2k is
    Port (
    Port (
       clk   : in  std_logic;
       clk   : in  std_logic;
       rst   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
 
       addr  : in  std_logic_vector (10 downto 0);
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       rw       : in  std_logic;
       wdata : in  std_logic_vector (7 downto 0)
       data_in  : in  std_logic_vector (7 downto 0);
 
       data_out : out std_logic_vector (7 downto 0)
    );
    );
end ram_2k;
end ram_2k;
 
 
architecture rtl of ram_2k is
architecture rtl of ram_2k is
 
 
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    INIT_3E => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
    INIT_3E => x"0822CEDFBC8B300F27FFFF8CCCDFBE49584F4AAF80E64AAE431FCADF9F6EC8DF",
    INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
    INIT_3F => x"00FFB2FFC2FFBEFFBAFFB6FFC6FFB2FFC2DF9F6E42EE1F37F16E44AEC4EC1034"
    )
    )
 
 
    port map (
    port map (
          do     => rdata,
          do     => data_out,
          dop(0) => dp,
          dop(0) => dp,
          addr   => addr,
          addr   => addr,
          clk    => clk,
          clk    => clk,
          di     => wdata,
          di     => data_in,
          dip(0) => dp,
          dip(0) => dp,
          en     => cs,
          en     => cs,
          ssr    => rst,
          ssr    => rst,
          we     => we
          we     => we
        );
        );

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