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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Diff between revs 165 and 177

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Line 126... Line 126...
library unisim;
library unisim;
   use unisim.vcomponents.all;
   use unisim.vcomponents.all;
 
 
entity system09 is
entity system09 is
  port(
  port(
    CLKA         : in  Std_Logic;  -- 100MHz Clock input
    sysclk         : in  Std_Logic;  -- 100MHz Clock input
    SW2_N        : in  Std_logic;  -- Master Reset input (active low)
    RESET_N      : in  Std_logic;  -- Master Reset input (active low)
    SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
    NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
 
    -- RS232 Port
    -- RS232 Port
    RS232_RXD    : in  Std_Logic;
  --RS232_CTS    : in  std_logic;       
    RS232_TXD    : out Std_Logic;
  --RS232_RTS    : out std_logic;  
 
    RS232_RXD    : in  Std_Logic;  -- RS-232 data in
    -- Status 7 segment LED
    RS232_TXD    : out Std_Logic   -- RS-232 data out
    S            : out std_logic_vector(7 downto 0)
 
 
 
-- CPU Debug Interface signals
-- CPU Debug Interface signals
--    cpu_reset_o     : out Std_Logic;
--    cpu_reset_o     : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_clk_o       : out Std_Logic;
--    cpu_rw_o        : out std_logic;
--    cpu_rw_o        : out std_logic;
Line 162... Line 161...
architecture rtl of system09 is
architecture rtl of system09 is
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- constants
  -- constants
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
  constant SYS_CLK_FREQ         : natural := 100_000_000; -- FPGA System Clock (in Hz)
  -- SDRAM
 
  constant MEM_CLK_FREQ         : natural := 100_000; -- operating frequency of Memory in KHz
 
  constant SYS_CLK_DIV          : real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
 
  constant PIPE_EN              : boolean := false;  -- if true, enable pipelined read operations
 
  constant MAX_NOP              : natural := 10000;  -- number of NOPs before entering self-refresh
 
  constant MULTIPLE_ACTIVE_ROWS : boolean := false;  -- if true, allow an active row in each bank
 
  constant DATA_WIDTH           : natural := 16;     -- host & SDRAM data width
 
  constant NROWS                : natural := 8192;   -- number of rows in SDRAM array
 
  constant NCOLS                : natural := 512;    -- number of columns in SDRAM array
 
  constant HADDR_WIDTH          : natural := 24;     -- host-side address width
 
  constant SADDR_WIDTH          : natural := 13;     -- SDRAM-side address width
 
 
 
  constant SYS_CLK_FREQ         : natural := ((MEM_CLK_FREQ*2)/integer(SYS_CLK_DIV*2.0))*1000;  -- FPGA System Clock
 
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
 
  constant TRESET               : natural := 300;      -- min initialization interval (us)
 
  constant RST_CYCLES           : natural := 1+(TRESET*(MEM_CLK_FREQ/1_000));  -- SDRAM power-on initialization interval
 
 
 
  type hold_state_type is ( hold_release_state, hold_request_state );
 
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Signals
  -- Signals
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
  -- BOOT ROM
  -- BOOT ROM
  signal rom_cs         : Std_logic;
  signal rom_cs         : Std_logic;
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
 
 
  -- Flex Memory & Monitor Stack
  -- Flex Memory & Monitor Stack
Line 209... Line 191...
  signal DCD_n          : Std_Logic;
  signal DCD_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal RTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
  signal CTS_n          : Std_Logic;
 
 
  -- RAM
  -- RAM
  signal ram_cs         : std_logic; -- memory chip select
  signal ram1_cs         : std_logic;
  signal ram_data_out   : std_logic_vector(7 downto 0);
  signal ram1_data_out   : std_logic_vector(7 downto 0);
  signal ram_rd_req     : std_logic; -- ram read request (asynch set on ram read, cleared falling CPU clock edge)
  signal ram2_cs         : std_logic;
  signal ram_wr_req     : std_logic; -- ram write request (set on rising CPU clock edge, asynch clear on acknowledge) 
  signal ram2_data_out   : std_logic_vector(7 downto 0);
  signal ram_hold       : std_logic; -- hold off slow accesses
  signal ram3_cs         : std_logic;
  signal ram_release    : std_logic; -- Release ram hold
 
 
 
  -- CPU Interface signals
  -- CPU Interface signals
  signal cpu_reset      : Std_Logic;
  signal cpu_reset      : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_clk        : Std_Logic;
  signal cpu_rw         : std_logic;
  signal cpu_rw         : std_logic;
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  -- trap
  -- trap
  signal trap_cs        : std_logic;
  signal trap_cs        : std_logic;
  signal trap_data_out  : std_logic_vector(7 downto 0);
  signal trap_data_out  : std_logic_vector(7 downto 0);
  signal trap_irq       : std_logic;
  signal trap_irq       : std_logic;
 
 
  -- Peripheral Bus port
 
  signal pb_data_out   : std_logic_vector(7 downto 0);
 
  signal pb_cs         : std_logic;       -- peripheral bus chip select
 
  signal pb_wru        : std_logic;       -- upper byte write strobe
 
  signal pb_wrl        : std_logic;       -- lower byte write strobe
 
  signal pb_rdu        : std_logic;       -- upper byte read strobe
 
  signal pb_rdl        : std_logic;       -- lower byte read strobe
 
  signal pb_hold       : std_logic;       -- hold peripheral bus access
 
  signal pb_release    : std_logic;       -- release hold of peripheral bus
 
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
 
  signal pb_hold_state : hold_state_type;
 
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
 
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
 
 
 
  signal rst_i         : std_logic;     -- internal reset signal
  signal rst_i         : std_logic;     -- internal reset signal
  signal clk_i         : std_logic;     -- internal master clock signal
  signal clk_i         : std_logic;     -- internal master clock signal
 
 
  -- signals that go through the SDRAM host-side interface
 
  signal opBegun       : std_logic;        -- SDRAM operation started indicator
 
  signal earlyBegun    : std_logic;        -- SDRAM operation started indicator
 
  signal ramDone       : std_logic;        -- SDRAM operation complete indicator
 
  signal rdDone        : std_logic;        -- SDRAM read operation complete indicator
 
  signal wrDone        : std_logic;        -- SDRAM write operation complete indicator
 
  signal hAddr         : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
 
  signal hDIn          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
 
  signal hDOut         : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
 
  signal hRd           : std_logic;        -- host-side read control signal
 
  signal hWr           : std_logic;        -- host-side write control signal
 
  signal hUds          : std_logic;        -- host-side upper data strobe
 
  signal hLds          : std_logic;        -- host-side lower data strobe
 
  signal rdPending     : std_logic;        -- read operation pending in SDRAM pipeline
 
  type ram_type is (ram_state_0,
 
                    ram_state_rd1, ram_state_rd2,
 
                    ram_state_wr1,
 
                                                  ram_state_3 );
 
  signal ram_state     : ram_type;
 
 
 
         signal flash_ce_n   :  std_logic;
 
    signal rs232_cts    :   Std_Logic;
    signal rs232_cts    :   Std_Logic;
    signal rs232_rts    :  Std_Logic;
    signal rs232_rts    :  Std_Logic;
 
 
--  signal BaudCount   : std_logic_vector(5 downto 0);
 
 
 
  signal CountL        : std_logic_vector(23 downto 0);
 
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal clk_count     : natural range 0 to CPU_CLK_DIV;
  signal Clk25         : std_logic;
  signal Clk25         : std_logic;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
Line 352... Line 295...
    data_out    : out std_logic_vector (7 downto 0);
    data_out    : out std_logic_vector (7 downto 0);
    data_in    : in  std_logic_vector (7 downto 0)
    data_in    : in  std_logic_vector (7 downto 0)
  );
  );
end component;
end component;
 
 
 
----------------------------------------
 
--
 
-- 32KBytes Block RAM 0000
 
-- $0000 - $7FFF
 
--
 
----------------------------------------
 
 
 
component ram_32k
 
  Port (
 
    clk      : in  std_logic;
 
    rst      : in  std_logic;
 
    cs       : in  std_logic;
 
    rw       : in  std_logic;
 
    addr     : in  std_logic_vector (14 downto 0);
 
    data_out    : out std_logic_vector (7 downto 0);
 
    data_in    : in  std_logic_vector (7 downto 0)
 
  );
 
end component;
 
 
 
 
 
----------------------------------------
 
--
 
-- 16KBytes Block RAM 8000
 
-- $8000 - $BFFF
 
--
 
----------------------------------------
 
 
 
component ram_16k
 
  Port (
 
    clk      : in  std_logic;
 
    rst      : in  std_logic;
 
    cs       : in  std_logic;
 
    rw       : in  std_logic;
 
    addr     : in  std_logic_vector (13 downto 0);
 
    data_out    : out std_logic_vector (7 downto 0);
 
    data_in    : in  std_logic_vector (7 downto 0)
 
  );
 
end component;
 
 
-----------------------------------------------------------------
-----------------------------------------------------------------
--
--
-- 6850 Compatible ACIA / UART
-- 6850 Compatible ACIA / UART
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
Line 453... Line 435...
    data_in  : in  std_logic_vector(7 downto 0);
    data_in  : in  std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(7 downto 0)
    data_out : out std_logic_vector(7 downto 0)
  );
  );
end component;
end component;
 
 
 
----------------------------------------
--
--
-- Clock buffer
-- Clock buffer
--
--
 
----------------------------------------
 
 
component BUFG
component BUFG
   Port (
   Port (
     i: in std_logic;
     i: in std_logic;
     o: out std_logic
     o: out std_logic
  );
  );
end component;
end component;
 
 
begin
begin
 
 
 
  clk_i <= sysclk;
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- Instantiation of internal components
  -- Instantiation of internal components
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
  my_cpu : cpu09
  my_cpu : cpu09
Line 509... Line 493...
      addr      => cpu_addr(12 downto 0),
      addr      => cpu_addr(12 downto 0),
      data_out     => flex_data_out,
      data_out     => flex_data_out,
      data_in     => cpu_data_out
      data_in     => cpu_data_out
    );
    );
 
 
 
  my_32k : ram_32k
 
    port map (
 
      clk       => cpu_clk,
 
      rst       => cpu_reset,
 
      cs        => ram1_cs,
 
      rw        => cpu_rw,
 
      addr      => cpu_addr(14 downto 0),
 
      data_out     => ram1_data_out,
 
      data_in     => cpu_data_out
 
    );
 
 
 
  my_16k : ram_16k
 
    port map (
 
      clk       => cpu_clk,
 
      rst       => cpu_reset,
 
      cs        => ram2_cs,
 
      rw        => cpu_rw,
 
      addr      => cpu_addr(13 downto 0),
 
      data_out     => ram2_data_out,
 
      data_in     => cpu_data_out
 
    );
 
 
  my_acia  : acia6850
  my_acia  : acia6850
    port map (
    port map (
      clk       => cpu_clk,
      clk       => cpu_clk,
      rst       => cpu_reset,
      rst       => cpu_reset,
      cs        => acia_cs,
      cs        => acia_cs,
Line 602... Line 608...
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
  mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
                     dat_addr,
                     dat_addr,
                     rom_data_out,
                     rom_data_out,
                     flex_data_out,
                     flex_data_out,
                     acia_data_out,
                     acia_data_out,
                     pb_data_out,
 
                     timer_data_out,
                     timer_data_out,
                     trap_data_out,
                     trap_data_out,
                     ram_data_out
                     ram1_data_out, ram2_data_out
                     )
                     )
  begin
  begin
    cpu_data_in <= (others=>'0');
    cpu_data_in <= (others=>'0');
    dat_cs      <= '0';
    dat_cs      <= '0';
    rom_cs      <= '0';
    rom_cs      <= '0';
    flex_cs     <= '0';
    flex_cs     <= '0';
    acia_cs     <= '0';
    acia_cs     <= '0';
    timer_cs    <= '0';
    timer_cs    <= '0';
    trap_cs     <= '0';
    trap_cs     <= '0';
    pb_cs       <= '0';
    ram1_cs      <= '0';
    ram_cs      <= '0';
    ram2_cs      <= '0';
 
 
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
    if cpu_addr( 15 downto 8 ) = "11111111" then  -- $FFxx
      cpu_data_in <= rom_data_out;
      cpu_data_in <= rom_data_out;
      dat_cs      <= cpu_vma;              -- write DAT
      dat_cs      <= cpu_vma;              -- write DAT
      rom_cs      <= cpu_vma;              -- read  ROM
      rom_cs      <= cpu_vma;              -- read  ROM
Line 702... Line 707...
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
    elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
      cpu_data_in <= flex_data_out;
      cpu_data_in <= flex_data_out;
      flex_cs     <= cpu_vma;
      flex_cs     <= cpu_vma;
 
 
    --
    --
 
    -- 32k RAM $00000 - $07FFF
 
    --
 
    elsif dat_addr(7 downto 1) = "0000000" then -- $00000 - $07FFF
 
      cpu_data_in <= ram1_data_out;
 
      ram1_cs     <= cpu_vma;
 
 
 
    --
 
    -- 16k RAM $08000 - $0BFFF
 
    --
 
    elsif dat_addr(7 downto 1) = "0000100" then -- $08000 - $0BFFF
 
      cpu_data_in <= ram2_data_out;
 
      ram2_cs     <= cpu_vma;
 
 
 
    --
    -- Everything else is RAM
    -- Everything else is RAM
    --
    --
    else
    else
      cpu_data_in <= ram_data_out;
      cpu_data_in <= (others => '0');
      ram_cs      <= cpu_vma;
      ram3_cs      <= cpu_vma;
    end if;
    end if;
 
 
  end process;
  end process;
 
 
  --
  --
  -- Interrupts and other bus control signals
  -- Interrupts and other bus control signals
  --
  --
  interrupts : process( SW3_N,
  interrupts : process( NMI_N,
                      pb_cs, pb_hold, pb_release, ram_hold,
 
                      acia_irq,
                      acia_irq,
                      trap_irq,
                      trap_irq,
                      timer_irq
                      timer_irq
                      )
                      )
  begin
  begin
    pb_hold    <= pb_cs and (not pb_release);
 
    cpu_irq    <= acia_irq;
    cpu_irq    <= acia_irq;
    cpu_nmi    <= trap_irq or not( SW3_N );
    cpu_nmi    <= trap_irq or not( NMI_N );
    cpu_firq   <= timer_irq;
    cpu_firq   <= timer_irq;
    cpu_halt   <= '0';
    cpu_halt   <= '0';
    cpu_hold   <= pb_hold or ram_hold;
    cpu_hold   <= '0'; -- pb_hold or ram_hold;
    FLASH_CE_N <= '1';
 
  end process;
 
 
 
  --
 
  -- Flash 7 segment LEDS
 
  --
 
  my_led_flasher: process( clk_i, rst_i, CountL )
 
  begin
 
    if rst_i = '1' then
 
         CountL <= "000000000000000000000000";
 
    elsif rising_edge(clk_i) then
 
         CountL <= CountL + 1;
 
    end if;
 
    --S(7 downto 0) <= CountL(23 downto 16);
 
  end process;
  end process;
 
 
  --
  --
  -- Generate CPU & Pixel Clock from Memory Clock
  -- Generate CPU & Pixel Clock from Memory Clock
  --
  --
Line 765... Line 768...
  end process;
  end process;
 
 
  --
  --
  -- Reset button and reset timer
  -- Reset button and reset timer
  --
  --
  my_switch_assignments : process( rst_i, SW2_N)
  my_switch_assignments : process( rst_i, RESET_N)
  begin
  begin
    rst_i <= not SW2_N;
    rst_i <= RESET_N;
    cpu_reset <= rst_i;
    cpu_reset <= rst_i;
  end process;
  end process;
 
 
  --
  --
  -- RS232 signals:
  -- RS232 signals:
Line 783... Line 786...
    dcd_n     <= '0';
    dcd_n     <= '0';
    RS232_TXD <= txd;
    RS232_TXD <= txd;
    RS232_RTS <= rts_n;
    RS232_RTS <= rts_n;
  end process;
  end process;
 
 
  --
 
  -- CPU read data request on rising CPU clock edge
 
  --
 
  ram_read_request: process( hRd, cpu_clk, ram_cs, cpu_rw, ram_release )
 
  begin
 
    if hRd = '1' then
 
      ram_rd_req   <= '0';
 
    elsif rising_edge(cpu_clk) then
 
      if (ram_cs = '1') and (cpu_rw = '1') and (ram_release = '1') then
 
        ram_rd_req   <= '1';
 
      end if;
 
    end if;
 
  end process;
 
 
 
  --
 
  -- CPU write data to RAM valid on rising CPU clock edge
 
  --
 
  ram_write_request: process( hWr, cpu_clk, ram_cs, cpu_rw, ram_release )
 
  begin
 
    if hWr = '1' then
 
       ram_wr_req   <= '0';
 
    elsif rising_edge(cpu_clk) then
 
      if (ram_cs = '1') and (cpu_rw = '0') and (ram_release = '1') then
 
        ram_wr_req   <= '1';
 
      end if;
 
    end if;
 
  end process;
 
 
 
  status_leds : process( rst_i, cpu_reset)
 
  begin
 
    S(7) <= rst_i;
 
    S(6) <= cpu_reset;
 
    S(2) <= countL(23);
 
    S(3) <= countL(22);
 
         S(4) <= countL(21);
 
         S(5) <= countL(20);
 
         S(1) <= '1'; -- countL(19);
 
         S(0) <= '0'; -- countL(18);
 
    --S(7 downto 4) <= "0000";
 
  end process;
 
 
 
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--  debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
--                      cpu_halt, cpu_hold,
--                      cpu_halt, cpu_hold,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_firq, cpu_irq, cpu_nmi,
--                      cpu_addr, cpu_data_out, cpu_data_in )
--                      cpu_addr, cpu_data_out, cpu_data_in )
--  begin
--  begin

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