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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Diff between revs 177 and 178

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Rev 177 Rev 178
Line 126... Line 126...
library unisim;
library unisim;
   use unisim.vcomponents.all;
   use unisim.vcomponents.all;
 
 
entity system09 is
entity system09 is
  port(
  port(
    sysclk         : in  Std_Logic;  -- 100MHz Clock input
    sysclk         : in  Std_Logic;  -- 125MHz Clock input
    RESET_N      : in  Std_logic;  -- Master Reset input (active low)
    RESET_N      : in  Std_logic;  -- Master Reset input (active low)
    NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
    NMI_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
 
 
    -- RS232 Port
    -- RS232 Port
  --RS232_CTS    : in  std_logic;       
  --RS232_CTS    : in  std_logic;       
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architecture rtl of system09 is
architecture rtl of system09 is
 
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- constants
  -- constants
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  constant SYS_CLK_FREQ         : natural := 100_000_000; -- FPGA System Clock (in Hz)
  constant SYS_CLK_FREQ         : natural := 125_000_000; -- FPGA System Clock (in Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_FREQ         : natural := 25_000_000;  -- CPU Clock (Hz)
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant CPU_CLK_DIV          : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant BAUD_RATE            : integer := 57600;     -- Baud Rate
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
  constant ACIA_CLK_FREQ        : integer := BAUD_RATE * 16;
 
 

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