Line 3... |
Line 3... |
-- S Y N T H E Z I A B L E System09 - SOC.
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
--
|
--
|
-- www.OpenCores.Org - February 2007
|
-- www.OpenCores.Org - February 2007
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- File name : System09_Xess_XSA-3S1000.vhd
|
-- File name : system09.vhd
|
--
|
--
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Designed with Xilinx XC3S1000 Spartan 3 FPGA.
|
-- Designed with Digilent Zybo Z20.
|
-- Implemented With XESS XSA-3S1000 FPGA board.
|
-- ==========================================================================
|
-- *** Note ***
|
-- Setup/Buttons
|
-- This configuration can run Flex9 however it only has
|
-- RS232 - connect a RS-232 Pmod to JE (upper row)
|
-- 32k bytes of user memory and the VDU is monochrome
|
-- Configure terminal for 57600 baud 8-N-1, hardware handshake
|
-- The design needs to be updated to use the SDRAM on
|
--
|
-- the XSA-3S1000 board.
|
-- Slide Switches - selects the nibble to display on the 4 LEDs
|
-- This configuration also lacks a DAT so cannot use
|
-- 0000 - CPU Address 3 to 0
|
-- the RAM Disk features of SYS09BUG.
|
-- 0001 - CPU Address 7 to 4
|
|
-- 0010 - CPU Address 11 to 8
|
|
-- 0011 - CPU Address 15 to 12
|
|
-- 0100 - CPU Data 3 to 0
|
|
-- 0101 - CPU Data 7 to 4
|
|
--
|
|
-- Push buttons
|
|
-- BTN3 BTN2 BTN1 BTN0
|
|
-- (unused) Single NMI RESET
|
|
-- Step
|
|
--
|
|
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
|
|
--
|
|
-- Memory Map :
|
|
--
|
|
-- $0000 - User program RAM (32K Bytes)
|
|
-- $8000 - User program RAM (16K Bytes)
|
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
|
-- $E000 - ACIA (SWTPc)
|
|
-- $E050 - Timer
|
|
-- $E060 - Bus trap
|
|
-- $F000 - Sys09Bug monitor Program (4K Bytes)
|
|
-- ==========================================================================
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Dependencies : ieee.Std_Logic_1164
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
-- unisim.vcomponents
|
-- unisim.vcomponents
|
--
|
--
|
-- Uses : mon_rom (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
|
-- Uses : mon_rom (sys09swt.vhd) SWTPc S-Bug 1.7 Monitor ROM
|
-- cpu09 (cpu09.vhd) CPU core
|
-- cpu09 (cpu09.vhd) CPU core
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- timer (timer.vhd) Interrupt timer
|
-- timer (timer.vhd) Interrupt timer
|
-- trap (trap.vhd) Bus condition trap logic
|
-- trap (trap.vhd) Bus condition trap logic
|
-- flex_ram (flex9_ram8k_b16.vhd) Flex operating system
|
-- flex_ram (flex9ram.vhd) Flex operating system
|
|
-- ram_16K (ram16k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
--
|
--
|
--
|
|
-- Author : John E. Kent
|
|
-- dilbert57@opencores.org
|
|
--
|
|
-- Memory Map :
|
|
--
|
|
-- $0000 - User program RAM (32K Bytes)
|
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
|
-- $E000 - ACIA (SWTPc)
|
|
-- $E010 - Reserved for FD1771 FDC (SWTPc)
|
|
-- $E050 - Timer
|
|
-- $E060 - Bus trap
|
|
-- $E070 - Reserced for Parallel I/O (B5-X300)
|
|
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
|
|
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
|
|
-- $F000 - Sys09Bug monitor Program (4K Bytes)
|
|
--
|
|
--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
--===========================================================================--
|
--===========================================================================--
|
-- Version 0.1 - 20 March 2003
|
-- Version 0.1 - Jan 20, 2021
|
-- Version 0.2 - 30 March 2003
|
-- Copied from the System09_Xess-XSA3S1000 vhdl
|
-- Version 0.3 - 29 April 2003
|
|
-- Version 0.4 - 29 June 2003
|
|
--
|
|
-- Version 0.5 - 19 July 2003
|
|
-- prints out "Hello World"
|
|
--
|
|
-- Version 0.6 - 5 September 2003
|
|
-- Runs SBUG
|
|
--
|
|
-- Version 1.0- 6 Sep 2003 - John Kent
|
|
-- Inverted SysClk
|
|
-- Initial release to Open Cores
|
|
--
|
|
-- Version 1.1 - 17 Jan 2004 - John Kent
|
|
-- Updated miniUart.
|
|
--
|
|
-- Version 1.2 - 25 Jan 2004 - John Kent
|
|
-- removed signals "test_alu" and "test_cc"
|
|
-- Trap hardware re-instated.
|
|
--
|
|
-- Version 1.3 - 11 Feb 2004 - John Kent
|
|
-- Designed forked off to produce System09_VDU
|
|
-- Added VDU component
|
|
-- VDU runs at 25MHz and divides the clock by 2 for the CPU
|
|
-- UART Runs at 57.6 Kbps
|
|
--
|
|
-- Version 2.0 - 2 September 2004 - John Kent
|
|
-- ported to Digilent Xilinx Spartan3 starter board
|
|
-- removed Compact Flash and Trap Logic.
|
|
-- Replaced SBUG with KBug9s
|
|
--
|
|
-- Version 3.0 - 29th August 2006 - John Kent
|
|
-- Adapted to XSA-3S1000 board.
|
|
-- Removed DAT and miniUART.
|
|
-- Used 32KBytes of Block RAM.
|
|
--
|
|
-- Version 3.1 - 15th January 2007 - John Kent
|
|
-- Modified vdu8 interface
|
|
-- Added a clock divider
|
|
--
|
|
-- Version 3.2 - 25th February 2007 - John Kent
|
|
-- reinstated ACIA_6850 and ACIA_Clock
|
|
-- Updated VDU8 & Keyboard with generic parameters
|
|
-- Defined Constants for clock speed calculations
|
|
--
|
|
-- Version 3.3 - 1st July 2007 - John Kent
|
|
-- Made VDU mono to save on one RAMB16
|
|
-- Used distributed memory for Key Map ROM to save one RAMB16
|
|
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
|
|
-- Added timer and trap logic
|
|
-- Added IDE Interface for Compact Flash
|
|
-- Replaced KBug9s and stack with Sys09Bug.
|
|
--
|
|
-- Version 4.0 - 1st February 2008 - John kent
|
|
-- Replaced Block RAM with SDRAM Interface
|
|
-- Modified Hold timing for SDRAM
|
|
-- Added CF and Ethernet interface
|
|
-- via the 16 bit peripheral bus at $E100
|
|
--
|
|
--===========================================================================--
|
--===========================================================================--
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
Line 126... |
Line 73... |
library unisim;
|
library unisim;
|
use unisim.vcomponents.all;
|
use unisim.vcomponents.all;
|
|
|
entity system09 is
|
entity system09 is
|
port(
|
port(
|
sysclk : in Std_Logic; -- 125MHz Clock input
|
CLKA : in Std_Logic; -- 125 MHz Clock input
|
RESET_N : in Std_logic; -- Master Reset input (active low)
|
|
NMI_N : in Std_logic; -- Non Maskable Interrupt input (active low)
|
|
|
|
-- RS232 Port
|
-- RS232 Port
|
--RS232_CTS : in std_logic;
|
RS232_RTS : out std_logic;
|
--RS232_RTS : out std_logic;
|
RS232_CTS : in std_logic;
|
RS232_RXD : in Std_Logic; -- RS-232 data in
|
RS232_RXD : in Std_Logic;
|
RS232_TXD : out Std_Logic -- RS-232 data out
|
RS232_TXD : out Std_Logic;
|
|
|
-- CPU Debug Interface signals
|
-- slide switches
|
-- cpu_reset_o : out Std_Logic;
|
sw : in std_logic_vector(3 downto 0);
|
-- cpu_clk_o : out Std_Logic;
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
-- cpu_rw_o : out std_logic;
|
btn : in std_logic_vector(3 downto 0);
|
-- cpu_vma_o : out std_logic;
|
-- Status 4 LEDs
|
-- cpu_halt_o : out std_logic;
|
led : out std_logic_vector(3 downto 0)
|
-- cpu_hold_o : out std_logic;
|
|
-- cpu_firq_o : out std_logic;
|
|
-- cpu_irq_o : out std_logic;
|
|
-- cpu_nmi_o : out std_logic;
|
|
-- cpu_addr_o : out std_logic_vector(15 downto 0);
|
|
-- cpu_data_in_o : out std_logic_vector(7 downto 0);
|
|
-- cpu_data_out_o : out std_logic_vector(7 downto 0);
|
|
|
|
);
|
);
|
end system09;
|
end system09;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for System09
|
-- Architecture for System09
|
Line 161... |
Line 98... |
architecture rtl of system09 is
|
architecture rtl of system09 is
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
|
|
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
signal pbtn : std_logic_vector(3 downto 0);
|
|
signal NMI_N : std_logic;
|
|
signal RESET_N : std_logic;
|
|
signal SINGLE_STEP : std_logic;
|
|
|
-- BOOT ROM
|
-- BOOT ROM
|
signal rom_cs : Std_logic;
|
signal rom_cs : Std_logic;
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
Line 228... |
Line 171... |
signal trap_irq : std_logic;
|
signal trap_irq : std_logic;
|
|
|
signal rst_i : std_logic; -- internal reset signal
|
signal rst_i : std_logic; -- internal reset signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
|
|
signal rs232_cts : Std_Logic;
|
signal CountL : std_logic_vector(23 downto 0);
|
signal rs232_rts : Std_Logic;
|
|
|
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
|
|
|
|
|
component btn_debounce
|
|
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
|
|
CLK : in STD_LOGIC;
|
|
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
|
|
end component;
|
|
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
Line 435... |
Line 384... |
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0)
|
data_out : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
|
--
|
--
|
-- Clock buffer
|
-- Clock buffer
|
--
|
--
|
----------------------------------------
|
|
|
|
component BUFG
|
component BUFG
|
Port (
|
Port (
|
i: in std_logic;
|
i: in std_logic;
|
o: out std_logic
|
o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
clk_i <= sysclk;
|
--
|
|
-- pushbutton debounce
|
|
--
|
|
my_singlestep: btn_debounce
|
|
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
|
|
|
|
RESET_N <= pbtn(0); -- Right PB
|
|
NMI_N <= pbtn(1); -- Center PB
|
|
SINGLE_STEP <= pbtn(2); -- Left PB
|
|
|
|
--
|
|
-- Generate CPU & Pixel Clock from Memory Clock
|
|
--
|
|
NORMAL: if CLOCK_MODE = 0 generate
|
|
my_prescaler : process( clk_i, clk_count )
|
|
begin
|
|
if rising_edge( clk_i ) then
|
|
if clk_count = 0 then
|
|
clk_count <= CPU_CLK_DIV-1;
|
|
else
|
|
clk_count <= clk_count - 1;
|
|
end if;
|
|
if clk_count = 0 then
|
|
clk25 <= '0';
|
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
|
clk25 <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end generate;
|
|
SS: if CLOCK_MODE = 1 generate
|
|
clk25 <= SINGLE_STEP;
|
|
end generate;
|
|
|
|
--
|
|
-- Reset button and reset timer
|
|
--
|
|
my_switch_assignments : process( rst_i, RESET_N)
|
|
begin
|
|
rst_i <= RESET_N;
|
|
cpu_reset <= rst_i;
|
|
end process;
|
|
|
|
clk_i <= CLKA;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09
|
my_cpu : cpu09
|
Line 527... |
Line 518... |
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => acia_data_out,
|
data_out => acia_data_out,
|
irq => acia_irq,
|
irq => acia_irq,
|
RxC => acia_clk,
|
RxC => acia_clk,
|
TxC => acia_clk,
|
TxC => acia_clk,
|
RxD => rxd,
|
RxD => RS232_RXD,
|
TxD => txd,
|
TxD => RS232_TXD,
|
DCD_n => dcd_n,
|
DCD_n => dcd_n,
|
CTS_n => cts_n,
|
CTS_n => RS232_CTS,
|
RTS_n => rts_n
|
RTS_n => RS232_RTS
|
);
|
);
|
|
dcd_n <= '0';
|
|
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
Line 747... |
Line 739... |
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0'; -- pb_hold or ram_hold;
|
cpu_hold <= '0'; -- pb_hold or ram_hold;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Generate CPU & Pixel Clock from Memory Clock
|
-- Flash 7 segment LEDS
|
--
|
--
|
my_prescaler : process( clk_i, clk_count )
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
begin
|
begin
|
if rising_edge( clk_i ) then
|
if rst_i = '1' then
|
if clk_count = 0 then
|
CountL <= "000000000000000000000000";
|
clk_count <= CPU_CLK_DIV-1;
|
elsif rising_edge(clk_i) then
|
else
|
CountL <= CountL + 1;
|
clk_count <= clk_count - 1;
|
|
end if;
|
|
if clk_count = 0 then
|
|
clk25 <= '0';
|
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
|
clk25 <= '1';
|
|
end if;
|
|
end if;
|
end if;
|
|
--S(7 downto 0) <= CountL(23 downto 16);
|
end process;
|
end process;
|
|
|
--
|
|
-- Reset button and reset timer
|
|
--
|
|
my_switch_assignments : process( rst_i, RESET_N)
|
|
begin
|
|
rst_i <= RESET_N;
|
|
cpu_reset <= rst_i;
|
|
end process;
|
|
|
|
--
|
|
-- RS232 signals:
|
|
--
|
status_leds : process( rst_i, cpu_reset,cpu_addr, cpu_rw, sw)
|
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
|
|
begin
|
begin
|
rxd <= RS232_RXD;
|
case sw is
|
cts_n <= RS232_CTS;
|
when "0000" =>
|
dcd_n <= '0';
|
led(3 downto 0) <= cpu_addr(3 downto 0);
|
RS232_TXD <= txd;
|
when "0001" =>
|
RS232_RTS <= rts_n;
|
led(3 downto 0) <= cpu_addr(7 downto 4);
|
|
when "0010" =>
|
|
led(3 downto 0) <= cpu_addr(11 downto 8);
|
|
when "0011" =>
|
|
led(3 downto 0) <= cpu_addr(15 downto 12);
|
|
when "0100" =>
|
|
led(3 downto 0) <= cpu_data_in(3 downto 0);
|
|
when "0101" =>
|
|
led(3 downto 0) <= cpu_data_in(7 downto 4);
|
|
when others => led(3 downto 0) <= (others => '0');
|
|
end case;
|
end process;
|
end process;
|
|
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- cpu_halt, cpu_hold,
|
-- cpu_halt, cpu_hold,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|