| Line 76... |
Line 76... |
entity system09 is
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entity system09 is
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port(
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port(
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CLKA : in Std_Logic; -- 125 MHz Clock input
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CLKA : in Std_Logic; -- 125 MHz Clock input
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-- RS232 Port - via Pmod RS232
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-- RS232 Port - via Pmod RS232
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RS232_CTS : in Std_Logic;
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-- RS232_CTS : in Std_Logic;
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RS232_RTS : out Std_Logic;
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-- RS232_RTS : out Std_Logic;
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RS232_RXD : in Std_Logic;
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RS232_RXD : in Std_Logic;
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RS232_TXD : out Std_Logic;
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RS232_TXD : out Std_Logic;
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-- slide switches
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-- slide switches
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sw : in std_logic_vector(3 downto 0);
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sw : in std_logic_vector(3 downto 0);
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| Line 171... |
Line 171... |
signal trap_irq : std_logic;
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signal trap_irq : std_logic;
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signal rst_i : std_logic; -- internal reset signal
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signal rst_i : std_logic; -- internal reset signal
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signal clk_i : std_logic; -- internal master clock signal
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signal clk_i : std_logic; -- internal master clock signal
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signal CountL : std_logic_vector(23 downto 0);
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signal CountL : std_logic_vector(25 downto 0);
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal clk_count : natural range 0 to CPU_CLK_DIV;
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signal Clk25 : std_logic;
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signal Clk25 : std_logic;
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component btn_debounce
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component btn_debounce
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| Line 405... |
Line 405... |
my_singlestep: btn_debounce
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my_singlestep: btn_debounce
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port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
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port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
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RESET <= pbtn(0); -- Right PB
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RESET <= pbtn(0); -- Right PB
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NMI <= pbtn(1); -- Center PB
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NMI <= pbtn(1); -- Center PB
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SINGLE_STEP <= pbtn(2); -- Left PB
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--
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--
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-- Generate CPU & Pixel Clock from Memory Clock
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-- Generate CPU & Pixel Clock from Memory Clock
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--
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--
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NORMAL: if CLOCK_MODE = 0 generate
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my_prescaler : process( clk_i, clk_count )
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my_prescaler : process( clk_i, clk_count )
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begin
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begin
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if rising_edge( clk_i ) then
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if rising_edge( clk_i ) then
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if clk_count = 0 then
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if clk_count = 0 then
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clk_count <= CPU_CLK_DIV-1;
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clk_count <= CPU_CLK_DIV-1;
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| Line 426... |
Line 425... |
elsif clk_count = (CPU_CLK_DIV/2) then
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elsif clk_count = (CPU_CLK_DIV/2) then
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clk25 <= '1';
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clk25 <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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SS: if CLOCK_MODE = 1 generate
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clk25 <= SINGLE_STEP;
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end generate;
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--
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--
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-- Reset button and reset timer
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-- Reset button and reset timer
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--
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--
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my_switch_assignments : process( rst_i, RESET)
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my_switch_assignments : process( rst_i, RESET)
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| Line 528... |
Line 523... |
);
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);
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--
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--
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-- RS232 signals:
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-- RS232 signals:
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--
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--
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my_acia_assignments : process( RS232_RXD, RS232_CTS, TXD, RTS_n )
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my_acia_assignments : process( RS232_RXD, --RS232_CTS,
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TXD, RTS_n )
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begin
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begin
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RXD <= RS232_RXD;
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RXD <= RS232_RXD;
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CTS_n <= RS232_CTS;
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CTS_n <= '0'; -- not RS232_CTS;
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DCD_n <= '0';
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DCD_n <= '0';
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RS232_TXD <= TXD;
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RS232_TXD <= TXD;
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RS232_RTS <= RTS_n;
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-- RS232_RTS <= not RTS_n;
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end process;
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end process;
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my_ACIA_Clock : ACIA_Clock
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my_ACIA_Clock : ACIA_Clock
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generic map(
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generic map(
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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SYS_CLK_FREQ => SYS_CLK_FREQ,
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| Line 755... |
Line 751... |
-- Flash 7 segment LEDS
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-- Flash 7 segment LEDS
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--
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--
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my_led_flasher: process( clk_i, rst_i, CountL )
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my_led_flasher: process( clk_i, rst_i, CountL )
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begin
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begin
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if rst_i = '1' then
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if rst_i = '1' then
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CountL <= "000000000000000000000000";
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CountL <= "00000000000000000000000000";
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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CountL <= CountL + 1;
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CountL <= CountL + 1;
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end if;
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end if;
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--S(7 downto 0) <= CountL(23 downto 16);
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--S(7 downto 0) <= CountL(23 downto 16);
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end process;
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end process;
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status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
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status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
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begin
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begin
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case sw is
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case sw is
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when "0000" =>
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when "1000" =>
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led(3 downto 0) <= cpu_addr(3 downto 0);
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led(3 downto 0) <= cpu_addr(3 downto 0);
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when "0001" =>
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when "1001" =>
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led(3 downto 0) <= cpu_addr(7 downto 4);
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led(3 downto 0) <= cpu_addr(7 downto 4);
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when "0010" =>
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when "1010" =>
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led(3 downto 0) <= cpu_addr(11 downto 8);
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led(3 downto 0) <= cpu_addr(11 downto 8);
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when "0011" =>
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when "1011" =>
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led(3 downto 0) <= cpu_addr(15 downto 12);
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led(3 downto 0) <= cpu_addr(15 downto 12);
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when "0100" =>
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when "1100" =>
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led(3 downto 0) <= cpu_data_in(3 downto 0);
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led(3 downto 0) <= cpu_data_in(3 downto 0);
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when "0101" =>
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when "1101" =>
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led(3 downto 0) <= cpu_data_in(7 downto 4);
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led(3 downto 0) <= cpu_data_in(7 downto 4);
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when "0000" =>
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led(3) <= '0';
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led(2) <= CountL(24);
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led(1) <= cpu_reset;
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led(0) <= NMI;
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when others => led(3 downto 0) <= (others => '0');
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when others => led(3 downto 0) <= (others => '0');
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end case;
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end case;
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end process;
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end process;
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-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
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-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
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