--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
-- S Y N T H E Z I A B L E System09 - SOC.
|
--
|
--
|
-- www.OpenCores.Org - February 2007
|
-- www.OpenCores.Org - February 2007
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- File name : system09.vhd
|
-- File name : system09.vhd
|
--
|
--
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Purpose : Top level file for 6809 compatible system on a chip
|
-- Designed with Digilent Zybo Z20.
|
-- Designed with Digilent Zybo Z20.
|
-- ==========================================================================
|
-- ==========================================================================
|
-- Setup/Buttons
|
-- Setup/Buttons
|
-- RS232 - connect a RS-232 Pmod to JE (upper row)
|
-- RS232 - connect a RS-232 Pmod to JE (upper row)
|
-- Configure terminal for 57600 baud 8-N-1, hardware handshake
|
-- Configure terminal for 57600 baud 8-N-1, hardware handshake
|
--
|
--
|
-- Slide Switches - selects the nibble to display on the 4 LEDs
|
-- Slide Switches - selects the nibble to display on the 4 LEDs
|
-- 0000 - CPU Address 3 to 0
|
-- 0000 - CPU Address 3 to 0
|
-- 0001 - CPU Address 7 to 4
|
-- 0001 - CPU Address 7 to 4
|
-- 0010 - CPU Address 11 to 8
|
-- 0010 - CPU Address 11 to 8
|
-- 0011 - CPU Address 15 to 12
|
-- 0011 - CPU Address 15 to 12
|
-- 0100 - CPU Data 3 to 0
|
-- 0100 - CPU Data 3 to 0
|
-- 0101 - CPU Data 7 to 4
|
-- 0101 - CPU Data 7 to 4
|
--
|
--
|
-- Push buttons
|
-- Push buttons
|
-- BTN3 BTN2 BTN1 BTN0
|
-- BTN3 BTN2 BTN1 BTN0
|
-- (unused) Single NMI RESET
|
-- (unused) Single NMI RESET
|
-- Step
|
-- Step
|
--
|
--
|
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
|
-- Single-Step functionality is controlled by the CLOCK_MODE constant below
|
--
|
--
|
-- Memory Map :
|
-- Memory Map :
|
--
|
--
|
-- $0000 - User program RAM (32K Bytes)
|
-- $0000 - User program RAM (32K Bytes)
|
-- $8000 - User program RAM (16K Bytes)
|
-- $8000 - User program RAM (16K Bytes)
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
-- $C000 - Flex Operating System memory (8K Bytes)
|
-- $E000 - ACIA (SWTPc)
|
-- $E000 - ACIA (SWTPc)
|
-- $E050 - Timer
|
-- $E050 - Timer
|
-- $E060 - Bus trap
|
-- $E060 - Bus trap
|
-- $F000 - Sys09Bug monitor Program (4K Bytes)
|
-- $F000 - Sys09Bug monitor Program (4K Bytes)
|
-- ==========================================================================
|
-- ==========================================================================
|
--
|
--
|
-- Dependencies : ieee.Std_Logic_1164
|
-- Dependencies : ieee.Std_Logic_1164
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
-- unisim.vcomponents
|
-- unisim.vcomponents
|
--
|
--
|
-- Uses : mon_rom (sys09swt.vhd) SWTPc S-Bug 1.7 Monitor ROM
|
-- Uses : mon_rom (sys09swt.vhd) SWTPc S-Bug 1.7 Monitor ROM
|
-- cpu09 (cpu09.vhd) CPU core
|
-- cpu09 (cpu09.vhd) CPU core
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_6850 (acia6850.vhd) ACIA / UART
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- ACIA_Clock (ACIA_Clock.vhd) ACIA clock.
|
-- timer (timer.vhd) Interrupt timer
|
-- timer (timer.vhd) Interrupt timer
|
-- trap (trap.vhd) Bus condition trap logic
|
-- trap (trap.vhd) Bus condition trap logic
|
-- flex_ram (flex9ram.vhd) Flex operating system
|
-- flex_ram (flex9ram.vhd) Flex operating system
|
-- ram_16K (ram16k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_16K (ram16k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
-- ram_32K (ram32k_b16.vhd) 32 KBytes of Block RAM
|
--
|
--
|
--===========================================================================----
|
--===========================================================================----
|
--
|
--
|
-- Revision History:
|
-- Revision History:
|
--===========================================================================--
|
--===========================================================================--
|
-- Version 0.1 - Jan 20, 2021
|
-- Version 0.1 - Jan 20, 2021
|
-- Copied from the System09_Xess-XSA3S1000 vhdl
|
-- Copied from the System09_Xess-XSA3S1000 vhdl
|
--===========================================================================--
|
--===========================================================================--
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
library work;
|
library work;
|
use work.common.all;
|
use work.common.all;
|
library unisim;
|
library unisim;
|
use unisim.vcomponents.all;
|
use unisim.vcomponents.all;
|
|
|
entity system09 is
|
entity system09 is
|
port(
|
port(
|
CLKA : in Std_Logic; -- 125 MHz Clock input
|
CLKA : in Std_Logic; -- 125 MHz Clock input
|
|
|
-- RS232 Port - via Pmod RS232
|
-- RS232 Port - via Pmod RS232
|
RS232_CTS : in Std_Logic;
|
RS232_CTS : in Std_Logic;
|
RS232_RTS : out Std_Logic;
|
RS232_RTS : out Std_Logic;
|
RS232_RXD : in Std_Logic;
|
RS232_RXD : in Std_Logic;
|
RS232_TXD : out Std_Logic;
|
RS232_TXD : out Std_Logic;
|
|
|
-- TMDS_Clk_p : out std_logic;
|
-- TMDS_Clk_p : out std_logic;
|
-- TMDS_Clk_n : out std_logic;
|
-- TMDS_Clk_n : out std_logic;
|
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
|
-- TMDS_Data_p : out std_logic_vector(2 downto 0);
|
-- TMDS_Data_n : out std_logic_vector(2 downto 0);
|
-- TMDS_Data_n : out std_logic_vector(2 downto 0);
|
|
|
-- raw output from VDU8
|
-- CRTC output signals
|
red, green, blue, hsync, vsync, blank : out std_logic;
|
VGA_vsync_n : out Std_Logic;
|
|
VGA_hsync_n : out Std_Logic;
|
|
VGA_blue : out std_logic_vector(3 downto 0);
|
|
VGA_green : out std_logic_vector(3 downto 0);
|
|
VGA_red : out std_logic_vector(3 downto 0);
|
|
|
-- slide switches
|
-- slide switches
|
sw : in std_logic_vector(3 downto 0);
|
sw : in std_logic_vector(3 downto 0);
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
-- push buttons [Unused, Single-Step, NMI, RESET]
|
btn : in std_logic_vector(3 downto 0);
|
btn : in std_logic_vector(3 downto 0);
|
-- Status 4 LEDs
|
-- Status 4 LEDs
|
led : out std_logic_vector(3 downto 0)
|
led : out std_logic_vector(3 downto 0)
|
);
|
);
|
end system09;
|
end system09;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for System09
|
-- Architecture for System09
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture rtl of system09 is
|
architecture rtl of system09 is
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- constants
|
-- constants
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
|
constant CLOCK_MODE : natural := 0; -- 0 means normal, 1 means single-step
|
|
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
|
constant SYS_CLK_FREQ : natural := 125_000_000; -- FPGA System Clock (in Hz)
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_FREQ : natural := 25_000_000; -- CPU Clock (Hz)
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant CPU_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
constant VGA_CLK_FREQ : natural := 25_000_000; -- VGA Pixel Clock
|
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/CPU_CLK_FREQ);
|
constant VGA_CLK_DIV : natural := (SYS_CLK_FREQ/VGA_CLK_FREQ);
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant BAUD_RATE : integer := 57600; -- Baud Rate
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
constant ACIA_CLK_FREQ : integer := BAUD_RATE * 16;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
signal pbtn : std_logic_vector(3 downto 0);
|
signal pbtn : std_logic_vector(3 downto 0);
|
signal NMI : std_logic;
|
signal NMI : std_logic;
|
signal RESET : std_logic;
|
signal RESET : std_logic;
|
signal SINGLE_STEP : std_logic;
|
signal SINGLE_STEP : std_logic;
|
|
|
-- BOOT ROM
|
-- BOOT ROM
|
signal rom_cs : Std_logic;
|
signal rom_cs : Std_logic;
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
signal rom_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- Flex Memory & Monitor Stack
|
-- Flex Memory & Monitor Stack
|
signal flex_cs : Std_logic;
|
signal flex_cs : Std_logic;
|
signal flex_data_out : Std_Logic_Vector(7 downto 0);
|
signal flex_data_out : Std_Logic_Vector(7 downto 0);
|
|
|
-- ACIA/UART Interface signals
|
-- ACIA/UART Interface signals
|
signal acia_data_out : Std_Logic_Vector(7 downto 0);
|
signal acia_data_out : Std_Logic_Vector(7 downto 0);
|
signal acia_cs : Std_Logic;
|
signal acia_cs : Std_Logic;
|
signal acia_irq : Std_Logic;
|
signal acia_irq : Std_Logic;
|
signal acia_clk : Std_Logic;
|
signal acia_clk : Std_Logic;
|
signal RXD : Std_Logic;
|
signal RXD : Std_Logic;
|
signal TXD : Std_Logic;
|
signal TXD : Std_Logic;
|
signal DCD_n : Std_Logic;
|
signal DCD_n : Std_Logic;
|
signal RTS_n : Std_Logic;
|
signal RTS_n : Std_Logic;
|
signal CTS_n : Std_Logic;
|
signal CTS_n : Std_Logic;
|
|
|
-- RAM
|
-- RAM
|
signal ram1_cs : std_logic;
|
signal ram1_cs : std_logic;
|
signal ram1_data_out : std_logic_vector(7 downto 0);
|
signal ram1_data_out : std_logic_vector(7 downto 0);
|
signal ram2_cs : std_logic;
|
signal ram2_cs : std_logic;
|
signal ram2_data_out : std_logic_vector(7 downto 0);
|
signal ram2_data_out : std_logic_vector(7 downto 0);
|
signal ram3_cs : std_logic;
|
signal ram3_cs : std_logic;
|
|
|
-- CPU Interface signals
|
-- CPU Interface signals
|
signal cpu_reset : Std_Logic;
|
signal cpu_reset : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_clk : Std_Logic;
|
signal cpu_rw : std_logic;
|
signal cpu_rw : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_vma : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_halt : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_hold : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_firq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_irq : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_nmi : std_logic;
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_addr : std_logic_vector(15 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_in : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
signal cpu_data_out : std_logic_vector(7 downto 0);
|
|
|
-- Dynamic Address Translation
|
-- Dynamic Address Translation
|
signal dat_cs : std_logic;
|
signal dat_cs : std_logic;
|
signal dat_addr : std_logic_vector(7 downto 0);
|
signal dat_addr : std_logic_vector(7 downto 0);
|
|
|
-- Video Display Unit (single-bit for each RGB color)
|
-- Video Display Unit
|
signal vdu_cs : std_logic;
|
signal vdu_cs : std_logic;
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vdu_data_out : std_logic_vector(7 downto 0);
|
signal vga_red_o : std_logic;
|
signal vga_red_o : std_logic;
|
signal vga_green_o : std_logic;
|
signal vga_green_o : std_logic;
|
signal vga_blue_o : std_logic;
|
signal vga_blue_o : std_logic;
|
signal vga_blank_o : std_logic; -- new signal
|
|
-- original VGA interface
|
|
signal vga_vsync_n : Std_Logic;
|
|
signal vga_hsync_n : Std_Logic;
|
|
signal VGA_blue : std_logic_vector(7 downto 0);
|
|
signal VGA_green : std_logic_vector(7 downto 0);
|
|
signal VGA_red : std_logic_vector(7 downto 0);
|
|
signal vid_pData : std_logic_vector(23 downto 0);
|
|
signal serial_clk_unused : std_logic;
|
signal serial_clk_unused : std_logic;
|
-- timer
|
-- timer
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_data_out : std_logic_vector(7 downto 0);
|
signal timer_cs : std_logic;
|
signal timer_cs : std_logic;
|
signal timer_irq : std_logic;
|
signal timer_irq : std_logic;
|
|
|
-- trap
|
-- trap
|
signal trap_cs : std_logic;
|
signal trap_cs : std_logic;
|
signal trap_data_out : std_logic_vector(7 downto 0);
|
signal trap_data_out : std_logic_vector(7 downto 0);
|
signal trap_irq : std_logic;
|
signal trap_irq : std_logic;
|
|
|
signal rst_i : std_logic; -- internal reset signal
|
signal rst_i : std_logic; -- internal reset signal
|
signal clk_i : std_logic; -- internal master clock signal
|
signal clk_i : std_logic; -- internal master clock signal
|
|
|
signal CountL : std_logic_vector(25 downto 0);
|
signal CountL : std_logic_vector(25 downto 0);
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal clk_count : natural range 0 to CPU_CLK_DIV;
|
signal Clk25 : std_logic;
|
signal Clk25 : std_logic;
|
signal vga_clk : std_logic;
|
signal vga_clk : std_logic;
|
|
|
component btn_debounce
|
component btn_debounce
|
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
|
Port ( BTN_I : in STD_LOGIC_VECTOR (3 downto 0);
|
CLK : in STD_LOGIC;
|
CLK : in STD_LOGIC;
|
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
|
BTN_O : out STD_LOGIC_VECTOR (3 downto 0));
|
end component;
|
end component;
|
|
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- CPU09 CPU core
|
-- CPU09 CPU core
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component cpu09
|
component cpu09
|
port (
|
port (
|
clk: in std_logic;
|
clk: in std_logic;
|
rst: in std_logic;
|
rst: in std_logic;
|
vma: out std_logic;
|
vma: out std_logic;
|
addr: out std_logic_vector(15 downto 0);
|
addr: out std_logic_vector(15 downto 0);
|
rw: out std_logic; -- Asynchronous memory interface
|
rw: out std_logic; -- Asynchronous memory interface
|
data_out: out std_logic_vector(7 downto 0);
|
data_out: out std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
data_in: in std_logic_vector(7 downto 0);
|
irq: in std_logic;
|
irq: in std_logic;
|
firq: in std_logic;
|
firq: in std_logic;
|
nmi: in std_logic;
|
nmi: in std_logic;
|
halt: in std_logic;
|
halt: in std_logic;
|
hold: in std_logic
|
hold: in std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 4K Block RAM Monitor ROM
|
-- 4K Block RAM Monitor ROM
|
-- $F000 - $FFFF
|
-- $F000 - $FFFF
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component mon_rom
|
component mon_rom
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (11 downto 0);
|
addr : in std_logic_vector (11 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 8KBytes Block RAM for FLEX9
|
-- 8KBytes Block RAM for FLEX9
|
-- $C000 - $DFFF
|
-- $C000 - $DFFF
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component flex_ram
|
component flex_ram
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (12 downto 0);
|
addr : in std_logic_vector (12 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 32KBytes Block RAM 0000
|
-- 32KBytes Block RAM 0000
|
-- $0000 - $7FFF
|
-- $0000 - $7FFF
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component ram_32k
|
component ram_32k
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (14 downto 0);
|
addr : in std_logic_vector (14 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- 16KBytes Block RAM 8000
|
-- 16KBytes Block RAM 8000
|
-- $8000 - $BFFF
|
-- $8000 - $BFFF
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component ram_16k
|
component ram_16k
|
Port (
|
Port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic_vector (13 downto 0);
|
addr : in std_logic_vector (13 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_out : out std_logic_vector (7 downto 0);
|
data_in : in std_logic_vector (7 downto 0)
|
data_in : in std_logic_vector (7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- 6850 Compatible ACIA / UART
|
-- 6850 Compatible ACIA / UART
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component acia6850
|
component acia6850
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- miniUART Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
addr : in Std_Logic; -- Register Select
|
addr : in Std_Logic; -- Register Select
|
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
data_in : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
RxC : in Std_Logic; -- Receive Baud Clock
|
RxC : in Std_Logic; -- Receive Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
RxD : in Std_Logic; -- Receive Data
|
RxD : in Std_Logic; -- Receive Data
|
TxD : out Std_Logic; -- Transmit Data
|
TxD : out Std_Logic; -- Transmit Data
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
CTS_n : in Std_Logic; -- Clear To Send
|
CTS_n : in Std_Logic; -- Clear To Send
|
RTS_n : out Std_Logic -- Request To send
|
RTS_n : out Std_Logic -- Request To send
|
);
|
);
|
end component;
|
end component;
|
|
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
--
|
--
|
-- ACIA Clock divider
|
-- ACIA Clock divider
|
--
|
--
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
|
|
component ACIA_Clock
|
component ACIA_Clock
|
generic (
|
generic (
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
SYS_CLK_FREQ : integer := SYS_CLK_FREQ;
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
ACIA_CLK_FREQ : integer := ACIA_CLK_FREQ
|
);
|
);
|
port (
|
port (
|
clk : in Std_Logic; -- System Clock Input
|
clk : in Std_Logic; -- System Clock Input
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
ACIA_clk : out Std_logic -- ACIA Clock output
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Video Display Unit.
|
-- Video Display Unit.
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component vdu8
|
component vdu8
|
generic(
|
generic(
|
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
|
VDU_CLK_FREQ : integer := CPU_CLK_FREQ; -- HZ
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
VGA_CLK_FREQ : integer := VGA_CLK_FREQ; -- HZ
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_HOR_CHARS : integer := 80; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_VER_CHARS : integer := 25; -- CHARACTERS
|
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
|
VGA_PIX_PER_CHAR : integer := 8; -- PIXELS
|
VGA_LIN_PER_CHAR : integer := 16; -- LINES
|
VGA_LIN_PER_CHAR : integer := 16; -- LINES
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_BACK_PORCH : integer := 40; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_SYNC : integer := 96; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_HOR_FRONT_PORCH : integer := 24; -- PIXELS
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_BACK_PORCH : integer := 13; -- LINES
|
VGA_VER_SYNC : integer := 2; -- LINES
|
VGA_VER_SYNC : integer := 2; -- LINES
|
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
|
VGA_VER_FRONT_PORCH : integer := 35 -- LINES
|
);
|
);
|
port(
|
port(
|
-- control register interface
|
-- control register interface
|
vdu_clk : in std_logic; -- CPU Clock - 25MHz
|
vdu_clk : in std_logic; -- CPU Clock - 25MHz
|
vdu_rst : in std_logic;
|
vdu_rst : in std_logic;
|
vdu_cs : in std_logic;
|
vdu_cs : in std_logic;
|
vdu_rw : in std_logic;
|
vdu_rw : in std_logic;
|
vdu_addr : in std_logic_vector(2 downto 0);
|
vdu_addr : in std_logic_vector(2 downto 0);
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
vdu_data_in : in std_logic_vector(7 downto 0);
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
vdu_data_out : out std_logic_vector(7 downto 0);
|
|
|
-- vga port connections
|
-- vga port connections
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_clk : in std_logic; -- VGA Pixel Clock - 25 MHz
|
vga_red_o : out std_logic;
|
vga_red_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_green_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_blue_o : out std_logic;
|
vga_blank_o : out std_logic; -- new signal "blank"
|
|
vga_hsync_o : out std_logic;
|
vga_hsync_o : out std_logic;
|
vga_vsync_o : out std_logic
|
vga_vsync_o : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer module
|
-- Timer module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component timer
|
component timer
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr : in std_logic;
|
addr : in std_logic;
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
------------------------------------------------------------
|
------------------------------------------------------------
|
--
|
--
|
-- Bus Trap logic
|
-- Bus Trap logic
|
--
|
--
|
------------------------------------------------------------
|
------------------------------------------------------------
|
|
|
component trap
|
component trap
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
vma : in std_logic;
|
vma : in std_logic;
|
addr : in std_logic_vector(15 downto 0);
|
addr : in std_logic_vector(15 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
irq : out std_logic
|
irq : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Dynamic Address Translation Registers
|
-- Dynamic Address Translation Registers
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
|
|
component dat_ram
|
component dat_ram
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
cs : in std_logic;
|
cs : in std_logic;
|
rw : in std_logic;
|
rw : in std_logic;
|
addr_lo : in std_logic_vector(3 downto 0);
|
addr_lo : in std_logic_vector(3 downto 0);
|
addr_hi : in std_logic_vector(3 downto 0);
|
addr_hi : in std_logic_vector(3 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0)
|
data_out : out std_logic_vector(7 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
--
|
--
|
-- Clock buffer
|
-- Clock buffer
|
--
|
--
|
|
|
component BUFG
|
component BUFG
|
Port (
|
Port (
|
i: in std_logic;
|
i: in std_logic;
|
o: out std_logic
|
o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
begin
|
begin
|
|
|
--
|
--
|
-- pushbutton debounce
|
-- pushbutton debounce
|
--
|
--
|
my_singlestep: btn_debounce
|
my_singlestep: btn_debounce
|
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
|
port map ( BTN_I => btn, CLK => CLKA, BTN_O => pbtn);
|
|
|
RESET <= pbtn(0); -- Right PB
|
RESET <= pbtn(0); -- Right PB
|
NMI <= pbtn(1); -- Center PB
|
NMI <= pbtn(1); -- Center PB
|
|
|
--
|
--
|
-- Generate CPU & Pixel Clock from Memory Clock
|
-- Generate CPU & Pixel Clock from Memory Clock
|
--
|
--
|
|
|
my_prescaler : process( clk_i, clk_count )
|
my_prescaler : process( clk_i, clk_count )
|
begin
|
begin
|
if rising_edge( clk_i ) then
|
if rising_edge( clk_i ) then
|
if clk_count = 0 then
|
if clk_count = 0 then
|
clk_count <= CPU_CLK_DIV-1;
|
clk_count <= CPU_CLK_DIV-1;
|
else
|
else
|
clk_count <= clk_count - 1;
|
clk_count <= clk_count - 1;
|
end if;
|
end if;
|
if clk_count = 0 then
|
if clk_count = 0 then
|
clk25 <= '0';
|
clk25 <= '0';
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
elsif clk_count = (CPU_CLK_DIV/2) then
|
clk25 <= '1';
|
clk25 <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Reset button and reset timer
|
-- Reset button and reset timer
|
--
|
--
|
my_switch_assignments : process( rst_i, RESET)
|
my_switch_assignments : process( rst_i, RESET)
|
begin
|
begin
|
rst_i <= RESET;
|
rst_i <= RESET;
|
cpu_reset <= rst_i;
|
cpu_reset <= rst_i;
|
end process;
|
end process;
|
|
|
clk_i <= CLKA;
|
clk_i <= CLKA;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
my_cpu : cpu09
|
my_cpu : cpu09
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
addr => cpu_addr(15 downto 0),
|
addr => cpu_addr(15 downto 0),
|
rw => cpu_rw,
|
rw => cpu_rw,
|
data_out => cpu_data_out,
|
data_out => cpu_data_out,
|
data_in => cpu_data_in,
|
data_in => cpu_data_in,
|
irq => cpu_irq,
|
irq => cpu_irq,
|
firq => cpu_firq,
|
firq => cpu_firq,
|
nmi => cpu_nmi,
|
nmi => cpu_nmi,
|
halt => cpu_halt,
|
halt => cpu_halt,
|
hold => cpu_hold
|
hold => cpu_hold
|
);
|
);
|
|
|
my_rom : mon_rom
|
my_rom : mon_rom
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => rom_cs,
|
cs => rom_cs,
|
rw => '1',
|
rw => '1',
|
addr => cpu_addr(11 downto 0),
|
addr => cpu_addr(11 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => rom_data_out
|
data_out => rom_data_out
|
);
|
);
|
|
|
my_flex : flex_ram
|
my_flex : flex_ram
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => flex_cs,
|
cs => flex_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(12 downto 0),
|
addr => cpu_addr(12 downto 0),
|
data_out => flex_data_out,
|
data_out => flex_data_out,
|
data_in => cpu_data_out
|
data_in => cpu_data_out
|
);
|
);
|
|
|
my_32k : ram_32k
|
my_32k : ram_32k
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => ram1_cs,
|
cs => ram1_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(14 downto 0),
|
addr => cpu_addr(14 downto 0),
|
data_out => ram1_data_out,
|
data_out => ram1_data_out,
|
data_in => cpu_data_out
|
data_in => cpu_data_out
|
);
|
);
|
|
|
my_16k : ram_16k
|
my_16k : ram_16k
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => ram2_cs,
|
cs => ram2_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(13 downto 0),
|
addr => cpu_addr(13 downto 0),
|
data_out => ram2_data_out,
|
data_out => ram2_data_out,
|
data_in => cpu_data_out
|
data_in => cpu_data_out
|
);
|
);
|
|
|
my_acia : acia6850
|
my_acia : acia6850
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => acia_cs,
|
cs => acia_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => acia_data_out,
|
data_out => acia_data_out,
|
irq => acia_irq,
|
irq => acia_irq,
|
RxC => acia_clk,
|
RxC => acia_clk,
|
TxC => acia_clk,
|
TxC => acia_clk,
|
RxD => RXD,
|
RxD => RXD,
|
TxD => TXD,
|
TxD => TXD,
|
DCD_n => DCD_n,
|
DCD_n => DCD_n,
|
CTS_n => CTS_n,
|
CTS_n => CTS_n,
|
RTS_n => RTS_n
|
RTS_n => RTS_n
|
);
|
);
|
|
|
--
|
--
|
-- RS232 signals:
|
-- RS232 signals:
|
--
|
--
|
my_acia_assignments : process( RS232_RXD, RS232_CTS,
|
my_acia_assignments : process( RS232_RXD, RS232_CTS,
|
TXD, RTS_n )
|
TXD, RTS_n )
|
begin
|
begin
|
RXD <= RS232_RXD;
|
RXD <= RS232_RXD;
|
CTS_n <= RS232_CTS;
|
CTS_n <= RS232_CTS;
|
DCD_n <= '0';
|
DCD_n <= '0';
|
RS232_TXD <= TXD;
|
RS232_TXD <= TXD;
|
RS232_RTS <= RTS_n;
|
RS232_RTS <= RTS_n;
|
end process;
|
end process;
|
|
|
my_ACIA_Clock : ACIA_Clock
|
my_ACIA_Clock : ACIA_Clock
|
generic map(
|
generic map(
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
SYS_CLK_FREQ => SYS_CLK_FREQ,
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
ACIA_CLK_FREQ => ACIA_CLK_FREQ
|
)
|
)
|
port map(
|
port map(
|
clk => clk_i,
|
clk => clk_i,
|
acia_clk => acia_clk
|
acia_clk => acia_clk
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Video Display Unit instantiation
|
-- Video Display Unit instantiation
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_vdu : vdu8
|
my_vdu : vdu8
|
generic map(
|
generic map(
|
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
|
VDU_CLK_FREQ => CPU_CLK_FREQ, -- HZ
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
VGA_CLK_FREQ => VGA_CLK_FREQ, -- HZ
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_HOR_CHARS => 80, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_VER_CHARS => 25, -- CHARACTERS
|
VGA_PIX_PER_CHAR => 8, -- PIXELS
|
VGA_PIX_PER_CHAR => 8, -- PIXELS
|
VGA_LIN_PER_CHAR => 16, -- LINES
|
VGA_LIN_PER_CHAR => 16, -- LINES
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_BACK_PORCH => 40, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_SYNC => 96, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_HOR_FRONT_PORCH => 24, -- PIXELS
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_BACK_PORCH => 13, -- LINES
|
VGA_VER_SYNC => 2, -- LINES
|
VGA_VER_SYNC => 2, -- LINES
|
VGA_VER_FRONT_PORCH => 35 -- LINES
|
VGA_VER_FRONT_PORCH => 35 -- LINES
|
)
|
)
|
port map(
|
port map(
|
-- Control Registers
|
-- Control Registers
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
vdu_clk => cpu_clk, -- 12.5 MHz System Clock in
|
vdu_rst => cpu_reset,
|
vdu_rst => cpu_reset,
|
vdu_cs => vdu_cs,
|
vdu_cs => vdu_cs,
|
vdu_rw => cpu_rw,
|
vdu_rw => cpu_rw,
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_addr => cpu_addr(2 downto 0),
|
vdu_data_in => cpu_data_out,
|
vdu_data_in => cpu_data_out,
|
vdu_data_out => vdu_data_out,
|
vdu_data_out => vdu_data_out,
|
-- vga port connections
|
-- vga port connections
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_clk => vga_clk, -- 25 MHz VDU pixel clock
|
vga_red_o => red,
|
vga_red_o => vga_red_o,
|
vga_green_o => green,
|
vga_green_o => vga_green_o,
|
vga_blue_o => blue,
|
vga_blue_o => vga_blue_o,
|
vga_blank_o => blank, -- new signal
|
vga_hsync_o => VGA_hsync_n,
|
vga_hsync_o => hsync,
|
vga_vsync_o => VGA_vsync_n
|
vga_vsync_o => vsync
|
|
);
|
);
|
|
--
|
|
-- VGA ouputs
|
|
--
|
|
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
|
|
begin
|
|
VGA_red(0) <= vga_red_o;
|
|
VGA_red(1) <= vga_red_o;
|
|
VGA_red(2) <= vga_red_o;
|
|
VGA_red(3) <= vga_red_o;
|
|
VGA_green(0) <= vga_green_o;
|
|
VGA_green(1) <= vga_green_o;
|
|
VGA_green(2) <= vga_green_o;
|
|
VGA_green(3) <= vga_green_o;
|
|
VGA_blue(0) <= vga_blue_o;
|
|
VGA_blue(1) <= vga_blue_o;
|
|
VGA_blue(2) <= vga_blue_o;
|
|
VGA_blue(3) <= vga_blue_o;
|
|
end process;
|
|
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Timer Module
|
-- Timer Module
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_timer : timer
|
my_timer : timer
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => timer_cs,
|
cs => timer_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr => cpu_addr(0),
|
addr => cpu_addr(0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => timer_data_out,
|
data_out => timer_data_out,
|
irq => timer_irq
|
irq => timer_irq
|
);
|
);
|
|
|
----------------------------------------
|
----------------------------------------
|
--
|
--
|
-- Bus Trap Interrupt logic
|
-- Bus Trap Interrupt logic
|
--
|
--
|
----------------------------------------
|
----------------------------------------
|
my_trap : trap
|
my_trap : trap
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => trap_cs,
|
cs => trap_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
vma => cpu_vma,
|
vma => cpu_vma,
|
addr => cpu_addr,
|
addr => cpu_addr,
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => trap_data_out,
|
data_out => trap_data_out,
|
irq => trap_irq
|
irq => trap_irq
|
);
|
);
|
|
|
my_dat : dat_ram
|
my_dat : dat_ram
|
port map (
|
port map (
|
clk => cpu_clk,
|
clk => cpu_clk,
|
rst => cpu_reset,
|
rst => cpu_reset,
|
cs => dat_cs,
|
cs => dat_cs,
|
rw => cpu_rw,
|
rw => cpu_rw,
|
addr_hi => cpu_addr(15 downto 12),
|
addr_hi => cpu_addr(15 downto 12),
|
addr_lo => cpu_addr(3 downto 0),
|
addr_lo => cpu_addr(3 downto 0),
|
data_in => cpu_data_out,
|
data_in => cpu_data_out,
|
data_out => dat_addr(7 downto 0)
|
data_out => dat_addr(7 downto 0)
|
);
|
);
|
|
|
cpu_clk_buffer : BUFG
|
cpu_clk_buffer : BUFG
|
port map(
|
port map(
|
i => Clk25,
|
i => Clk25,
|
o => cpu_clk
|
o => cpu_clk
|
);
|
);
|
|
vga_clk_buffer : BUFG
|
|
port map(
|
|
i => Clk25,
|
|
o => vga_clk
|
|
);
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- Process to decode memory map
|
-- Process to decode memory map
|
--
|
--
|
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
|
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
mem_decode: process( cpu_addr, cpu_rw, cpu_vma,
|
dat_addr,
|
dat_addr,
|
rom_data_out,
|
rom_data_out,
|
flex_data_out,
|
flex_data_out,
|
acia_data_out,
|
acia_data_out,
|
vdu_data_out,
|
vdu_data_out,
|
timer_data_out,
|
timer_data_out,
|
trap_data_out,
|
trap_data_out,
|
ram1_data_out, ram2_data_out
|
ram1_data_out, ram2_data_out
|
)
|
)
|
begin
|
begin
|
cpu_data_in <= (others=>'0');
|
cpu_data_in <= (others=>'0');
|
dat_cs <= '0';
|
dat_cs <= '0';
|
rom_cs <= '0';
|
rom_cs <= '0';
|
flex_cs <= '0';
|
flex_cs <= '0';
|
acia_cs <= '0';
|
acia_cs <= '0';
|
vdu_cs <= '0';
|
vdu_cs <= '0';
|
timer_cs <= '0';
|
timer_cs <= '0';
|
trap_cs <= '0';
|
trap_cs <= '0';
|
ram1_cs <= '0';
|
ram1_cs <= '0';
|
ram2_cs <= '0';
|
ram2_cs <= '0';
|
|
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
if cpu_addr( 15 downto 8 ) = "11111111" then -- $FFxx
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
dat_cs <= cpu_vma; -- write DAT
|
dat_cs <= cpu_vma; -- write DAT
|
rom_cs <= cpu_vma; -- read ROM
|
rom_cs <= cpu_vma; -- read ROM
|
|
|
--
|
--
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
-- Sys09Bug Monitor ROM $F000 - $FFFF
|
--
|
--
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
|
cpu_data_in <= rom_data_out;
|
cpu_data_in <= rom_data_out;
|
rom_cs <= cpu_vma;
|
rom_cs <= cpu_vma;
|
|
|
--
|
--
|
-- IO Devices $E000 - $E7FF
|
-- IO Devices $E000 - $E7FF
|
--
|
--
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
|
case cpu_addr(11 downto 8) is
|
case cpu_addr(11 downto 8) is
|
--
|
--
|
-- SWTPC peripherals from $E000 to $E0FF
|
-- SWTPC peripherals from $E000 to $E0FF
|
--
|
--
|
when "0000" =>
|
when "0000" =>
|
case cpu_addr(7 downto 4) is
|
case cpu_addr(7 downto 4) is
|
--
|
--
|
-- Console Port ACIA $E000 - $E00F
|
-- Console Port ACIA $E000 - $E00F
|
--
|
--
|
when "0000" => -- $E000
|
when "0000" => -- $E000
|
cpu_data_in <= acia_data_out;
|
cpu_data_in <= acia_data_out;
|
acia_cs <= cpu_vma;
|
acia_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Reserved
|
-- Reserved
|
-- Floppy Disk Controller port $E010 - $E01F
|
-- Floppy Disk Controller port $E010 - $E01F
|
--
|
--
|
--
|
--
|
-- VDU port $E030 - $E03F
|
-- VDU port $E030 - $E03F
|
--
|
--
|
when "0011" => -- $E030
|
when "0011" => -- $E030
|
cpu_data_in <= vdu_data_out;
|
cpu_data_in <= vdu_data_out;
|
vdu_cs <= cpu_vma;
|
vdu_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
-- Reserved SWTPc MP-T Timer $E040 - $E04F
|
--
|
--
|
when "0100" => -- $E040
|
when "0100" => -- $E040
|
cpu_data_in <= (others=> '0');
|
cpu_data_in <= (others=> '0');
|
|
|
--
|
--
|
-- Timer $E050 - $E05F
|
-- Timer $E050 - $E05F
|
--
|
--
|
when "0101" => -- $E050
|
when "0101" => -- $E050
|
cpu_data_in <= timer_data_out;
|
cpu_data_in <= timer_data_out;
|
timer_cs <= cpu_vma;
|
timer_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Bus Trap Logic $E060 - $E06F
|
-- Bus Trap Logic $E060 - $E06F
|
--
|
--
|
when "0110" => -- $E060
|
when "0110" => -- $E060
|
cpu_data_in <= trap_data_out;
|
cpu_data_in <= trap_data_out;
|
trap_cs <= cpu_vma;
|
trap_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
|
-- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
|
--
|
--
|
|
|
--
|
--
|
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
|
-- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
|
--
|
--
|
|
|
--
|
--
|
-- Remaining 6 slots reserved for non SWTPc Peripherals
|
-- Remaining 6 slots reserved for non SWTPc Peripherals
|
--
|
--
|
when others => -- $E0A0 to $E0FF
|
when others => -- $E0A0 to $E0FF
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- $E200 to $EFFF reserved for future use
|
-- $E200 to $EFFF reserved for future use
|
--
|
--
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
--
|
--
|
-- Block RAM (32k) $00000 - $07FFF
|
-- Block RAM (32k) $00000 - $07FFF
|
--
|
--
|
elsif dat_addr(7 downto 3) = "00000" then -- $00000 - $07FFF
|
elsif dat_addr(7 downto 3) = "00000" then -- $00000 - $07FFF
|
cpu_data_in <= ram1_data_out;
|
cpu_data_in <= ram1_data_out;
|
ram1_cs <= cpu_vma;
|
ram1_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Block RAM (16k) $08000 - $0BFFF
|
-- Block RAM (16k) $08000 - $0BFFF
|
--
|
--
|
elsif dat_addr(7 downto 2) = "000010" then -- $08000 - $0BFFF
|
elsif dat_addr(7 downto 2) = "000010" then -- $08000 - $0BFFF
|
cpu_data_in <= ram2_data_out;
|
cpu_data_in <= ram2_data_out;
|
ram2_cs <= cpu_vma;
|
ram2_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Flex RAM (8k) $0C000 - $0DFFF
|
-- Flex RAM (8k) $0C000 - $0DFFF
|
--
|
--
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
|
cpu_data_in <= flex_data_out;
|
cpu_data_in <= flex_data_out;
|
flex_cs <= cpu_vma;
|
flex_cs <= cpu_vma;
|
|
|
--
|
--
|
-- Everything else is RAM
|
-- Everything else is RAM
|
--
|
--
|
else
|
else
|
cpu_data_in <= (others => '0');
|
cpu_data_in <= (others => '0');
|
ram3_cs <= cpu_vma;
|
ram3_cs <= cpu_vma;
|
end if;
|
end if;
|
|
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Interrupts and other bus control signals
|
-- Interrupts and other bus control signals
|
--
|
--
|
interrupts : process( NMI,
|
interrupts : process( NMI,
|
acia_irq,
|
acia_irq,
|
trap_irq,
|
trap_irq,
|
timer_irq
|
timer_irq
|
)
|
)
|
begin
|
begin
|
cpu_irq <= acia_irq;
|
cpu_irq <= acia_irq;
|
cpu_nmi <= trap_irq or NMI;
|
cpu_nmi <= trap_irq or NMI;
|
cpu_firq <= timer_irq;
|
cpu_firq <= timer_irq;
|
cpu_halt <= '0';
|
cpu_halt <= '0';
|
cpu_hold <= '0'; -- pb_hold or ram_hold;
|
cpu_hold <= '0'; -- pb_hold or ram_hold;
|
end process;
|
end process;
|
|
|
--
|
--
|
-- Flash 7 segment LEDS
|
-- Flash 7 segment LEDS
|
--
|
--
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
my_led_flasher: process( clk_i, rst_i, CountL )
|
begin
|
begin
|
if rst_i = '1' then
|
if rst_i = '1' then
|
CountL <= "00000000000000000000000000";
|
CountL <= "00000000000000000000000000";
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
CountL <= CountL + 1;
|
CountL <= CountL + 1;
|
end if;
|
end if;
|
--S(7 downto 0) <= CountL(23 downto 16);
|
--S(7 downto 0) <= CountL(23 downto 16);
|
end process;
|
end process;
|
|
|
status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
|
status_leds : process( rst_i, cpu_reset, cpu_addr, cpu_data_in, sw)
|
begin
|
begin
|
case sw is
|
case sw is
|
when "1000" =>
|
when "1000" =>
|
led(3 downto 0) <= cpu_addr(3 downto 0);
|
led(3 downto 0) <= cpu_addr(3 downto 0);
|
when "1001" =>
|
when "1001" =>
|
led(3 downto 0) <= cpu_addr(7 downto 4);
|
led(3 downto 0) <= cpu_addr(7 downto 4);
|
when "1010" =>
|
when "1010" =>
|
led(3 downto 0) <= cpu_addr(11 downto 8);
|
led(3 downto 0) <= cpu_addr(11 downto 8);
|
when "1011" =>
|
when "1011" =>
|
led(3 downto 0) <= cpu_addr(15 downto 12);
|
led(3 downto 0) <= cpu_addr(15 downto 12);
|
when "1100" =>
|
when "1100" =>
|
led(3 downto 0) <= cpu_data_in(3 downto 0);
|
led(3 downto 0) <= cpu_data_in(3 downto 0);
|
when "1101" =>
|
when "1101" =>
|
led(3 downto 0) <= cpu_data_in(7 downto 4);
|
led(3 downto 0) <= cpu_data_in(7 downto 4);
|
when "0000" =>
|
when "0000" =>
|
led(3) <= '0';
|
led(3) <= '0';
|
led(2) <= CountL(24);
|
led(2) <= CountL(24);
|
led(1) <= cpu_reset;
|
led(1) <= cpu_reset;
|
led(0) <= NMI;
|
led(0) <= NMI;
|
when others => led(3 downto 0) <= (others => '0');
|
when others => led(3 downto 0) <= (others => '0');
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- debug_proc : process( cpu_reset, cpu_clk, cpu_rw, cpu_vma,
|
-- cpu_halt, cpu_hold,
|
-- cpu_halt, cpu_hold,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_firq, cpu_irq, cpu_nmi,
|
-- cpu_addr, cpu_data_out, cpu_data_in )
|
-- cpu_addr, cpu_data_out, cpu_data_in )
|
-- begin
|
-- begin
|
-- cpu_reset_o <= cpu_reset;
|
-- cpu_reset_o <= cpu_reset;
|
-- cpu_clk_o <= cpu_clk;
|
-- cpu_clk_o <= cpu_clk;
|
-- cpu_rw_o <= cpu_rw;
|
-- cpu_rw_o <= cpu_rw;
|
-- cpu_vma_o <= cpu_vma;
|
-- cpu_vma_o <= cpu_vma;
|
-- cpu_halt_o <= cpu_halt;
|
-- cpu_halt_o <= cpu_halt;
|
-- cpu_hold_o <= cpu_hold;
|
-- cpu_hold_o <= cpu_hold;
|
-- cpu_firq_o <= cpu_firq;
|
-- cpu_firq_o <= cpu_firq;
|
-- cpu_irq_o <= cpu_irq;
|
-- cpu_irq_o <= cpu_irq;
|
-- cpu_nmi_o <= cpu_nmi;
|
-- cpu_nmi_o <= cpu_nmi;
|
-- cpu_addr_o <= cpu_addr;
|
-- cpu_addr_o <= cpu_addr;
|
-- cpu_data_out_o <= cpu_data_out;
|
-- cpu_data_out_o <= cpu_data_out;
|
-- cpu_data_in_o <= cpu_data_in;
|
-- cpu_data_in_o <= cpu_data_in;
|
-- end process;
|
-- end process;
|
|
|
end rtl; --===================== End of architecture =======================--
|
end rtl; --===================== End of architecture =======================--
|
|
|
|
|