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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_ZyboZ20/] [system09.vhd] - Diff between revs 202 and 208

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Line 268... Line 268...
  );
  );
end component;
end component;
 
 
----------------------------------------
----------------------------------------
--
--
 
-- Parameterized Block RAM
 
--
 
----------------------------------------
 
 
 
  component block_spram
 
    generic (
 
      dwidth : integer := 8;     -- parameterized data width
 
           awidth : integer := 16     -- parameterized address width
 
         );
 
         port (
 
      clk         : in std_logic;
 
           cs          : in std_logic; -- chip-select/enable
 
           addr        : in std_logic_vector(awidth-1 downto 0);
 
           rw          : in std_logic;
 
           data_in     : in std_logic_vector(dwidth-1 downto 0);
 
           data_out    : out std_logic_vector(dwidth-1 downto 0)
 
         );
 
  end component;
 
 
 
----------------------------------------
 
--
-- 32KBytes Block RAM 0000
-- 32KBytes Block RAM 0000
-- $0000 - $7FFF
-- $0000 - $7FFF
--
--
----------------------------------------
----------------------------------------
 
 
Line 544... Line 565...
      addr      => cpu_addr(12 downto 0),
      addr      => cpu_addr(12 downto 0),
      data_out     => flex_data_out,
      data_out     => flex_data_out,
      data_in     => cpu_data_out
      data_in     => cpu_data_out
    );
    );
 
 
  my_32k : ram_32k
  my_32k : block_spram
 
    generic map (dwidth => 8, awidth => 15)
    port map (
    port map (
      clk       => cpu_clk,
      clk       => cpu_clk,
      rst       => cpu_reset,
      --rst       => cpu_reset,
      cs        => ram1_cs,
      cs        => ram1_cs,
      rw        => cpu_rw,
      rw        => cpu_rw,
      addr      => cpu_addr(14 downto 0),
      addr      => cpu_addr(14 downto 0),
      data_out     => ram1_data_out,
      data_out     => ram1_data_out,
      data_in     => cpu_data_out
      data_in     => cpu_data_out
    );
    );
 
 
  my_16k : ram_16k
  my_16k : block_spram
 
    generic map (dwidth => 8, awidth => 14)
    port map (
    port map (
      clk       => cpu_clk,
      clk       => cpu_clk,
      rst       => cpu_reset,
      --rst       => cpu_reset,
      cs        => ram2_cs,
      cs        => ram2_cs,
      rw        => cpu_rw,
      rw        => cpu_rw,
      addr      => cpu_addr(13 downto 0),
      addr      => cpu_addr(13 downto 0),
      data_out     => ram2_data_out,
      data_out     => ram2_data_out,
      data_in     => cpu_data_out
      data_in     => cpu_data_out

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