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[/] [System09/] [trunk/] [rtl/] [System09_Xess_XSA-3S1000/] [System09_Xess_XSA-3S1000.vhd] - Diff between revs 95 and 99

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Rev 95 Rev 99
Line 24... Line 24...
--                  ieee.numeric_std
--                  ieee.numeric_std
--                  unisim.vcomponents
--                  unisim.vcomponents
--
--
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
--                  cpu09      (cpu09.vhd)          CPU core
--                  cpu09      (cpu09.vhd)          CPU core
--                  ACIA_6850  (ACIA_6850.vhd)      ACIA / UART
--                  ACIA_6850  (acia6850.vhd)      ACIA / UART
--                             (ACIA_RX.vhd)
 
--                             (ACIA_TX.vhd)
 
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
--                             (ps2_keyboard.vhd)
--                             (ps2_keyboard.vhd)
--                             (keymap_rom_slice.vhd) Key map table 
--                             (keymap_rom_slice.vhd) Key map table 
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
Line 365... Line 363...
 
 
component cpu09
component cpu09
  port (
  port (
         clk:        in std_logic;
         clk:        in std_logic;
    rst:      in        std_logic;
    rst:      in        std_logic;
    rw:      out        std_logic;              -- Asynchronous memory interface
 
    vma:             out        std_logic;
    vma:             out        std_logic;
    address:  out       std_logic_vector(15 downto 0);
    addr:  out  std_logic_vector(15 downto 0);
    data_in:  in        std_logic_vector(7 downto 0);
    rw:      out        std_logic;              -- Asynchronous memory interface
         data_out: out std_logic_vector(7 downto 0);
         data_out: out std_logic_vector(7 downto 0);
         halt:     in  std_logic;
    data_in:  in        std_logic_vector(7 downto 0);
         hold:     in  std_logic;
 
         irq:      in  std_logic;
         irq:      in  std_logic;
 
         firq:     in  std_logic;
         nmi:      in  std_logic;
         nmi:      in  std_logic;
         firq:     in  std_logic
         halt:     in  std_logic;
 
         hold:     in  std_logic
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
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--
--
-- 6850 Compatible ACIA / UART
-- 6850 Compatible ACIA / UART
--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
 
 
component ACIA_6850
component acia6850
  port (
  port (
     clk      : in  Std_Logic;  -- System Clock
     clk      : in  Std_Logic;  -- System Clock
     rst      : in  Std_Logic;  -- Reset input (active high)
     rst      : in  Std_Logic;  -- Reset input (active high)
     cs       : in  Std_Logic;  -- miniUART Chip Select
     cs       : in  Std_Logic;  -- miniUART Chip Select
     rw       : in  Std_Logic;  -- Read / Not Write
     rw       : in  Std_Logic;  -- Read / Not Write
 
     addr     : in  Std_Logic;  -- Register Select
 
     data_in  : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
 
     data_out : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
     irq      : out Std_Logic;  -- Interrupt
     irq      : out Std_Logic;  -- Interrupt
     Addr     : in  Std_Logic;  -- Register Select
 
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
 
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     RxC      : in  Std_Logic;  -- Receive Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
     RxD      : in  Std_Logic;  -- Receive Data
     RxD      : in  Std_Logic;  -- Receive Data
     TxD      : out Std_Logic;  -- Transmit Data
     TxD      : out Std_Logic;  -- Transmit Data
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
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--
--
-----------------------------------------------------------------
-----------------------------------------------------------------
 
 
component ACIA_Clock
component ACIA_Clock
  generic (
  generic (
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
     SYS_CLK_FREQ  : integer :=  SYS_Clock_Frequency;
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
          ACIA_CLK_FREQ : integer := ACIA_Clock_Frequency
  );
  );
  port (
  port (
     clk      : in  Std_Logic;  -- System Clock Input
     clk      : in  Std_Logic;  -- System Clock Input
          ACIA_clk : out Std_logic   -- ACIA Clock output
          acia_clk : out Std_logic   -- ACIA Clock output
  );
  );
end component;
end component;
 
 
 
 
----------------------------------------
----------------------------------------
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--
--
----------------------------------------
----------------------------------------
 
 
component keyboard
component keyboard
  generic(
  generic(
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
  KBD_CLK_FREQ : integer := CPU_Clock_Frequency
  );
  );
  port(
  port(
  clk             : in    std_logic;
  clk             : in    std_logic;
  rst             : in    std_logic;
  rst             : in    std_logic;
  cs              : in    std_logic;
  cs              : in    std_logic;
Line 649... Line 647...
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
 
 
my_cpu : cpu09  port map (
my_cpu : cpu09  port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
    rst       => cpu_reset,
    rst       => cpu_reset,
    rw       => cpu_rw,
 
    vma       => cpu_vma,
    vma       => cpu_vma,
    address   => cpu_addr(15 downto 0),
    addr   => cpu_addr(15 downto 0),
    data_in   => cpu_data_in,
    rw       => cpu_rw,
         data_out  => cpu_data_out,
         data_out  => cpu_data_out,
         halt      => cpu_halt,
    data_in   => cpu_data_in,
         hold      => cpu_hold,
 
         irq       => cpu_irq,
         irq       => cpu_irq,
 
         firq      => cpu_firq,
         nmi       => cpu_nmi,
         nmi       => cpu_nmi,
         firq      => cpu_firq
         halt      => cpu_halt,
 
         hold      => cpu_hold
  );
  );
 
 
my_rom : mon_rom port map (
my_rom : mon_rom port map (
       clk   => cpu_clk,
       clk   => cpu_clk,
                 rst   => cpu_reset,
                 rst   => cpu_reset,
Line 681... Line 679...
    addr      => cpu_addr(12 downto 0),
    addr      => cpu_addr(12 downto 0),
    data_out     => flex_data_out,
    data_out     => flex_data_out,
    data_in     => cpu_data_out
    data_in     => cpu_data_out
    );
    );
 
 
my_acia  : ACIA_6850 port map (
my_acia  : acia6850 port map (
         clk         => cpu_clk,
         clk         => cpu_clk,
         rst       => cpu_reset,
         rst       => cpu_reset,
    cs        => acia_cs,
    cs        => acia_cs,
         rw        => cpu_rw,
         rw        => cpu_rw,
 
    addr      => cpu_addr(0),
 
         data_in    => cpu_data_out,
 
         data_out   => acia_data_out,
    irq       => acia_irq,
    irq       => acia_irq,
    Addr      => cpu_addr(0),
 
         Datain    => cpu_data_out,
 
         DataOut   => acia_data_out,
 
         RxC       => acia_clk,
         RxC       => acia_clk,
         TxC       => acia_clk,
         TxC       => acia_clk,
         RxD       => rxd,
         RxD       => rxd,
         TxD       => txd,
         TxD       => txd,
         DCD_n     => dcd_n,
         DCD_n     => dcd_n,
Line 702... Line 701...
         );
         );
 
 
 
 
my_ACIA_Clock : ACIA_Clock
my_ACIA_Clock : ACIA_Clock
  generic map(
  generic map(
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
    SYS_CLK_FREQ  => SYS_Clock_Frequency,
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
         ACIA_CLK_FREQ => ACIA_Clock_Frequency
  )
  )
  port map(
  port map(
    clk        => Clk_i,
    clk        => Clk_i,
    acia_clk   => acia_clk
    acia_clk   => acia_clk
  );
  );
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-- PS/2 Keyboard Interface
-- PS/2 Keyboard Interface
--
--
----------------------------------------
----------------------------------------
my_keyboard : keyboard
my_keyboard : keyboard
   generic map (
   generic map (
        KBD_Clock_Frequency => CPU_Clock_frequency
        KBD_CLK_FREQ => CPU_Clock_frequency
        )
        )
   port map(
   port map(
        clk          => cpu_clk,
        clk          => cpu_clk,
        rst          => cpu_reset,
        rst          => cpu_reset,
        cs           => keyboard_cs,
        cs           => keyboard_cs,

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