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Line 11... |
-- Purpose : Implements a RS232 6850 compatible
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-- Purpose : Implements a RS232 6850 compatible
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-- Asynchronous Communications Interface Adapter (ACIA)
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-- Asynchronous Communications Interface Adapter (ACIA)
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--
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--
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-- Dependencies : ieee.std_logic_1164
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-- Dependencies : ieee.std_logic_1164
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-- ieee.numeric_std
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-- ieee.numeric_std
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-- unisim.vcomponents
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-- ieee.std_logic_unsigned
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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--
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--
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-- Email : dilbert57@opencores.org
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-- Email : dilbert57@opencores.org
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--
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--
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| Line 123... |
Line 123... |
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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--library unisim;
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use unisim.vcomponents.all;
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-- use unisim.vcomponents.all;
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|
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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-- Entity for ACIA_6850 --
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-- Entity for ACIA_6850 --
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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Line 338... |
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Generate Read / Write strobes.
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-- Generate Read / Write strobes.
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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ACIA_Read_Write : process(clk, ac_rst)
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acia_read_write : process(clk, ac_rst)
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begin
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begin
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if falling_edge(clk) then
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if falling_edge(clk) then
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if ac_rst = '1' then
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if rst = '1' then
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CtrlReg <= (others => '0');
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CtrlReg(1 downto 0) <= "11";
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CtrlReg(7 downto 2) <= (others => '0');
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TxReg <= (others => '0');
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TxReg <= (others => '0');
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RxRd <= '0';
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RxRd <= '0';
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TxWr <= '0';
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TxWr <= '0';
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StRd <= '0';
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StRd <= '0';
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else
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else
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