| Line 203... |
Line 203... |
----------------------------------------------------------------------
|
----------------------------------------------------------------------
|
--
|
--
|
-- IO address + 0 Write
|
-- IO address + 0 Write
|
--
|
--
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- RxIE |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-- RXIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- RxIEnb - Bit[7]
|
-- RxIEnb - Bit[7]
|
-- 0 - Rx Interrupt disabled
|
-- 0 - Rx Interrupt disabled
|
-- 1 - Rx Interrupt enabled
|
-- 1 - Rx Interrupt enabled
|
-- TxCtl - Bits[6..5]
|
-- TxCtl - Bits[6..5]
|
| Line 317... |
Line 317... |
begin
|
begin
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- ACIA Reset may be hardware or software
|
-- ACIA Reset may be hardware or software
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
|
|
acia_reset : process( clk, rst, ac_rst, dcd_n )
|
acia_reset : process( clk, rst, ac_rst, dcd_n )
|
begin
|
begin
|
--
|
--
|
-- ACIA reset Synchronous
|
-- ACIA reset Synchronous
|
-- Includes software reset
|
-- Includes software reset
|
| Line 333... |
Line 334... |
-- Transmitter reset
|
-- Transmitter reset
|
tx_rst <= ac_rst;
|
tx_rst <= ac_rst;
|
|
|
end process;
|
end process;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Generate Read / Write strobes.
|
-- Generate Read / Write strobes.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
acia_read_write : process(clk, ac_rst)
|
acia_read_write : process(clk, ac_rst)
|
| Line 392... |
Line 392... |
(RxIE and DCDInt) or
|
(RxIE and DCDInt) or
|
(TxIE and TxRdy);
|
(TxIE and TxRdy);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- ACIA Transmit Control
|
-- ACIA Transmit Control
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
acia_control : process(CtrlReg, TxDat)
|
acia_control : process(CtrlReg, TxDat)
|
| Line 443... |
Line 442... |
irq <= StatReg(7);
|
irq <= StatReg(7);
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- Data Carrier Detect Edge rising edge detect
|
-- Data Carrier Detect Edge rising edge detect
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
|
|
acia_dcd_edge : process( clk, ac_rst )
|
acia_dcd_edge : process( clk, ac_rst )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if ac_rst = '1' then
|
if ac_rst = '1' then
|
DCDDel <= '0';
|
DCDDel <= '0';
|
| Line 456... |
Line 456... |
DCDEdge <= DCD_n and (not DCDDel);
|
DCDEdge <= DCD_n and (not DCDDel);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- Data Carrier Detect Interrupt
|
-- Data Carrier Detect Interrupt
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
-- If Data Carrier is lost, an interrupt is generated
|
-- If Data Carrier is lost, an interrupt is generated
|
-- To clear the interrupt, first read the status register
|
-- To clear the interrupt, first read the status register
|
| Line 497... |
Line 496... |
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver Clock Edge Detection
|
-- Receiver Clock Edge Detection
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- A rising edge will produce a one clock cycle pulse
|
-- A rising edge will produce a one clock cycle pulse
|
--
|
|
acia_rx_clock_edge : process( clk, rx_rst )
|
acia_rx_clock_edge : process( clk, rx_rst )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
RxClkDel <= '0';
|
RxClkDel <= '0';
|
| Line 520... |
Line 518... |
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver Data Edge Detection
|
-- Receiver Data Edge Detection
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- A falling edge will produce a pulse on RxClk wide
|
-- A falling edge will produce a pulse on RxClk wide
|
--
|
|
acia_rx_data_edge : process( clk, rx_rst )
|
acia_rx_data_edge : process( clk, rx_rst )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
RxDatDel0 <= '0';
|
RxDatDel0 <= '0';
|
| Line 543... |
Line 541... |
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver Start / Stop
|
-- Receiver Start / Stop
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Enable the receive clock on detection of a start bit
|
-- Enable the receive clock on detection of a start bit
|
-- Disable the receive clock after a byte is received.
|
-- Disable the receive clock after a byte is received.
|
--
|
|
acia_rx_start_stop : process( clk, rx_rst )
|
acia_rx_start_stop : process( clk, rx_rst )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
RxEnable <= '0';
|
RxEnable <= '0';
|
| Line 569... |
Line 567... |
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver Clock Divider
|
-- Receiver Clock Divider
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Hold the Rx Clock divider in reset when the receiver is disabled
|
-- Hold the Rx Clock divider in reset when the receiver is disabled
|
-- Advance the count only on a rising Rx clock edge
|
-- Advance the count only on a rising Rx clock edge
|
--
|
|
acia_rx_clock_divide : process( clk, rx_rst )
|
acia_rx_clock_divide : process( clk, rx_rst )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
RxClkCnt <= (others => '0');
|
RxClkCnt <= (others => '0');
|
| Line 620... |
Line 618... |
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
|
|
acia_rx_receive : process( clk, rst )
|
acia_rx_receive : process( clk, rst )
|
begin
|
begin
|
if falling_edge( clk ) then
|
if falling_edge( clk ) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
FErr <= '0';
|
FErr <= '0';
|
| Line 704... |
Line 703... |
end process;
|
end process;
|
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Receiver Read process
|
-- Receiver Read process
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
acia_rx_read : process( clk, rst, RxRdy )
|
acia_rx_read : process( clk, rst, RxRdy )
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if rx_rst = '1' then
|
if rx_rst = '1' then
|
RxRdy <= '0';
|
RxRdy <= '0';
|
| Line 724... |
Line 724... |
RxRdy <= '1'; -- Flag RxRdy and read Shift Register
|
RxRdy <= '1'; -- Flag RxRdy and read Shift Register
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Transmit Clock Edge Detection
|
-- Transmit Clock Edge Detection
|
-- A falling edge will produce a one clock cycle pulse
|
-- A falling edge will produce a one clock cycle pulse
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
| Line 762... |
Line 761... |
end process;
|
end process;
|
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Transmit Baud Clock Selector
|
-- Transmit Baud Clock Selector
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC )
|
acia_tx_baud_clock_select : process( BdFmt, TxClkCnt, TxC )
|
begin
|
begin
|
-- BdFmt
|
-- BdFmt
|
-- 0 0 - Baud Clk divide by 1
|
-- 0 0 - Baud Clk divide by 1
|
-- 0 1 - Baud Clk divide by 16
|
-- 0 1 - Baud Clk divide by 16
|
| Line 793... |
Line 793... |
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
|
|
acia_tx_transmit : process( clk, tx_rst)
|
acia_tx_transmit : process( clk, tx_rst)
|
begin
|
begin
|
if falling_edge(clk) then
|
if falling_edge(clk) then
|
if tx_rst = '1' then
|
if tx_rst = '1' then
|
TxDat <= '1';
|
TxDat <= '1';
|
