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-- $Id: cpu09.vhd,v 1.2 2008-03-14 15:52:46 dilbert57 Exp $
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--===========================================================================--
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--===========================================================================----
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-- --
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--
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-- Synthesizable 6809 instruction compatible VHDL CPU core --
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-- S Y N T H E Z I A B L E CPU09 - 6809 compatible CPU Core
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-- --
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--
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--===========================================================================--
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-- www.OpenCores.Org - September 2003
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-- This core adheres to the GNU public license
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--
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--
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-- File name : cpu09.vhd
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-- File name : cpu09.vhd
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--
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--
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-- Purpose : 6809 CPU core
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-- Entity name : cpu09
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Purpose : 6809 instruction compatible CPU core written in VHDL
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-- ieee.std_logic_unsigned
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-- Not cycle compatible with the original 6809 CPU
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--
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--
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-- Uses : None
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-- Dependencies : ieee.std_logic_1164
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-- ieee.std_logic_unsigned
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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-- dilbert57@opencores.org
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--
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--
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--===========================================================================----
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-- Email : dilbert57@opencores.org
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--
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-- Web : http://opencores.org/project,system09
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--
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--
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-- Revision History:
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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--===========================================================================--
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--
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--
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-- Version 0.1 - 26 June 2003 - John Kent
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-- Version 0.1 - 26 June 2003 - John Kent
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-- Added extra level in state stack
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-- Added extra level in state stack
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-- fixed some calls to the extended addressing state
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-- fixed some calls to the extended addressing state
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Line 188... |
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entity cpu09 is
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entity cpu09 is
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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rst: in std_logic;
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rw: out std_logic;
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vma: out std_logic;
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vma: out std_logic;
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address: out std_logic_vector(15 downto 0);
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addr : out std_logic_vector(15 downto 0);
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data_in: in std_logic_vector(7 downto 0);
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rw : out std_logic;
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data_out: out std_logic_vector(7 downto 0);
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data_out: out std_logic_vector(7 downto 0);
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halt: in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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hold: in std_logic;
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irq: in std_logic;
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irq: in std_logic;
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firq: in std_logic;
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firq: in std_logic;
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nmi: in std_logic
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nmi : in std_logic;
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halt : in std_logic;
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hold : in std_logic
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);
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);
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end cpu09;
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end cpu09;
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architecture rtl of cpu09 is
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architecture rtl of cpu09 is
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-- Detect Edge of NMI interrupt
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-- Detect Edge of NMI interrupt
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--
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--
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------------------------------------
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------------------------------------
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--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
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--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
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nmi_handler : process( clk )
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nmi_handler : process( rst, clk )
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begin
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begin
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if clk'event and clk='0' then
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if rst='1' then
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if rst='1' then
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nmi_req <= '0';
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nmi_req <= '0';
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else
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elsif clk'event and clk='0' then
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if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
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if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
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nmi_req <= '1';
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nmi_req <= '1';
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else
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else
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if (nmi='0') and (nmi_ack='1') then
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if (nmi='0') and (nmi_ack='1') then
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nmi_req <= '0';
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nmi_req <= '0';
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else
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nmi_req <= nmi_req;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
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addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
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begin
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begin
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case addr_ctrl is
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case addr_ctrl is
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when idle_ad =>
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when idle_ad =>
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address <= "1111111111111111";
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vma <= '0';
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vma <= '0';
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addr <= "1111111111111111";
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rw <= '1';
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rw <= '1';
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when fetch_ad =>
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when fetch_ad =>
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address <= pc;
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vma <= '1';
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vma <= '1';
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addr <= pc;
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rw <= '1';
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rw <= '1';
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when read_ad =>
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when read_ad =>
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address <= ea;
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vma <= '1';
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vma <= '1';
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addr <= ea;
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rw <= '1';
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rw <= '1';
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when write_ad =>
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when write_ad =>
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address <= ea;
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vma <= '1';
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vma <= '1';
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addr <= ea;
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rw <= '0';
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rw <= '0';
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when pushs_ad =>
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when pushs_ad =>
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address <= sp;
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vma <= '1';
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vma <= '1';
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addr <= sp;
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rw <= '0';
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rw <= '0';
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when pulls_ad =>
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when pulls_ad =>
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address <= sp;
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vma <= '1';
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vma <= '1';
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addr <= sp;
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rw <= '1';
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rw <= '1';
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when pushu_ad =>
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when pushu_ad =>
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address <= up;
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vma <= '1';
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vma <= '1';
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addr <= up;
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rw <= '0';
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rw <= '0';
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when pullu_ad =>
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when pullu_ad =>
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address <= up;
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vma <= '1';
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vma <= '1';
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addr <= up;
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rw <= '1';
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rw <= '1';
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when int_hi_ad =>
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when int_hi_ad =>
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address <= "111111111111" & iv & "0";
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vma <= '1';
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vma <= '1';
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addr <= "111111111111" & iv & "0";
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rw <= '1';
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rw <= '1';
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when int_lo_ad =>
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when int_lo_ad =>
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address <= "111111111111" & iv & "1";
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vma <= '1';
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vma <= '1';
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addr <= "111111111111" & iv & "1";
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rw <= '1';
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rw <= '1';
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when others =>
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when others =>
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address <= "1111111111111111";
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vma <= '0';
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vma <= '0';
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addr <= "1111111111111111";
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rw <= '1';
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rw <= '1';
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end case;
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end case;
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end process;
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end process;
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--------------------------------
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--------------------------------
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when pshs_state =>
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when pshs_state =>
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-- decrement sp if any registers to be pushed
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-- decrement sp if any registers to be pushed
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left_ctrl <= sp_left;
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left_ctrl <= sp_left;
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right_ctrl <= one_right;
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right_ctrl <= one_right;
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alu_ctrl <= alu_sub16;
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alu_ctrl <= alu_sub16;
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-- idle address
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addr_ctrl <= idle_ad;
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dout_ctrl <= cc_dout;
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if ea(7 downto 0) = "00000000" then
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if ea(7 downto 0) = "00000000" then
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sp_ctrl <= latch_sp;
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sp_ctrl <= latch_sp;
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else
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else
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sp_ctrl <= load_sp;
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sp_ctrl <= load_sp;
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end if;
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end if;
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