OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [ioport.vhd] - Diff between revs 66 and 99

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 66 Rev 99
Line 1... Line 1...
--===========================================================================----
--===========================================================================--
--
--                                                                           --
--  S Y N T H E Z I A B L E    ioport - 2 x 8 bit parallel I/O port
--  ioport.vhd - Synthesizable Dual Bidirectionsal I/O Port                  --
--
--                                                                           --
--  www.OpenCores.Org - September 2003
--===========================================================================--
--  This core adheres to the GNU public license  
 
--
--
-- File name      : ioport.vhd
-- File name      : ioport.vhd
--
--
-- Purpose        : dual 8 bit I/O module for System09
--  Purpose        : Implements a dual 8 bit bidirectional I/O port
--
--
-- Dependencies   : ieee.Std_Logic_1164
--  Dependencies   : ieee.std_logic_1164
--                  ieee.std_logic_unsigned
--                  ieee.std_logic_unsigned
--
--                   unisim.vcomponents
-- Uses           : None
 
--
--
-- Author         : John E. Kent      
-- Author         : John E. Kent      
--                  dilbert57@opencores.org      
 
--
--
--===========================================================================----
--  Email          : dilbert57@opencores.org      
 
--
 
--  Web            : http://opencores.org/project,system09
--
--
-- Revision History:
--  ioport.vhd is a dual bi-directional 8 bit I/O port written in VHDL.
 
-- 
 
--  Copyright (C) 2002 - 2010 John Kent
 
--
 
--  This program is free software: you can redistribute it and/or modify
 
--  it under the terms of the GNU General Public License as published by
 
--  the Free Software Foundation, either version 3 of the License, or
 
--  (at your option) any later version.
 
--
 
--  This program is distributed in the hope that it will be useful,
 
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
 
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
--  GNU General Public License for more details.
 
--
 
--  You should have received a copy of the GNU General Public License
 
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
--
 
--===========================================================================--
 
--                                                                           --
 
--                              Revision  History                            --
 
--                                                                           --
--===========================================================================--
--===========================================================================--
--
--
-- Version 0.1 - 11 Oct 2002
-- Version  Author        Date               Description
--   Used a loop counter for data direction & read port signals
-- 0.1      John E. Kent  11 October 2002    Used a loop counter for 
-- Version 0.2 - 5 Sept 2003
--                                           data direction & read port signals
--   Reduced to 2 x 8 bit ports
-- 0.2      John E. Kent  5 September 2003   Reduced to 2 x 8 bit ports
-- Version 1.0 - 6 Sept 2003 - John Kent
-- 1.0      John E. Kent  6 September 2003   Changed Clock Edge
--   Realeased to open Cores
-- 1.1      John E. Kent  25 Februrary 2007  Modified sensitivity lists
--   changed Clock Edge
-- 1.2      John E. Kent  30 May 2010        Updated Header, added unisim library
-- Version 1.1 - 25 Feb 2007 - John Kent
 
--   modified sensitivity lists
 
--
--
--===========================================================================
--===========================================================================
--
--
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
 
library unisim;
 
  use unisim.vcomponents.all;
 
 
entity ioport is
entity ioport is
        port (
        port (
         clk       : in  std_logic;
         clk       : in  std_logic;
    rst       : in  std_logic;
    rst       : in  std_logic;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.