OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [trunk/] [rtl/] [VHDL/] [pia_timer.vhd] - Diff between revs 99 and 118

Show entire file | Details | Blame | View Log

Rev 99 Rev 118
Line 120... Line 120...
signal ca1         : std_logic;
signal ca1         : std_logic;
signal ca1_del     : std_logic;
signal ca1_del     : std_logic;
signal ca1_rise    : std_logic;
signal ca1_rise    : std_logic;
signal ca1_fall    : std_logic;
signal ca1_fall    : std_logic;
signal ca1_edge    : std_logic;
signal ca1_edge    : std_logic;
signal irqa1       : std_logic;
signal irqa1       : std_logic := '0';
 
 
signal ca2         : std_logic;
signal ca2         : std_logic;
signal ca2_del     : std_logic;
signal ca2_del     : std_logic;
signal ca2_rise    : std_logic;
signal ca2_rise    : std_logic;
signal ca2_fall    : std_logic;
signal ca2_fall    : std_logic;
signal ca2_edge    : std_logic;
signal ca2_edge    : std_logic;
signal irqa2       : std_logic;
signal irqa2       : std_logic := '0';
signal ca2_out     : std_logic;
signal ca2_out     : std_logic;
 
 
signal cb1         : std_logic;
signal cb1         : std_logic;
signal cb1_del     : std_logic;
signal cb1_del     : std_logic;
signal cb1_rise    : std_logic;
signal cb1_rise    : std_logic;
signal cb1_fall    : std_logic;
signal cb1_fall    : std_logic;
signal cb1_edge    : std_logic;
signal cb1_edge    : std_logic;
signal irqb1       : std_logic;
signal irqb1       : std_logic := '0';
 
 
signal cb2         : std_logic;
signal cb2         : std_logic;
signal cb2_del     : std_logic;
signal cb2_del     : std_logic;
signal cb2_rise    : std_logic;
signal cb2_rise    : std_logic;
signal cb2_fall    : std_logic;
signal cb2_fall    : std_logic;
signal cb2_edge    : std_logic;
signal cb2_edge    : std_logic;
signal irqb2       : std_logic;
signal irqb2       : std_logic := '0';
signal cb2_out     : std_logic;
signal cb2_out     : std_logic;
 
 
-- 74193 down counter
-- 74193 down counter
signal timer       : std_logic_vector(7 downto 0);
signal timer       : std_logic_vector(7 downto 0);
 
 
Line 164... Line 164...
                                                        porta_data, portb_data,
                                                        porta_data, portb_data,
                                                        porta_ctrl, portb_ctrl,
                                                        porta_ctrl, portb_ctrl,
                                                   pa,         pb )
                                                   pa,         pb )
variable count : integer;
variable count : integer;
begin
begin
 
        data_out <= "00000000";
 
        porta_read <= '0';
 
        portb_read <= '0';
 
 
      case addr is
      case addr is
             when "00" =>
             when "00" =>
                    for count in 0 to 7 loop
                    for count in 0 to 7 loop
                           if porta_ctrl(2) = '0' then
                           if porta_ctrl(2) = '0' then
                                  data_out(count) <= porta_ddr(count);
                                  data_out(count) <= porta_ddr(count);
Line 208... Line 212...
                    data_out <= irqb1 & irqb2 & portb_ctrl;
                    data_out <= irqb1 & irqb2 & portb_ctrl;
                         porta_read <= '0';
                         porta_read <= '0';
                         portb_read <= '0';
                         portb_read <= '0';
 
 
                  when others =>
                  when others =>
                    data_out <= "00000000";
      null;
                         porta_read <= '0';
 
                         portb_read <= '0';
 
 
 
                end case;
                end case;
 
 
end process;
end process;
 
 
---------------------------------
---------------------------------
--
--
-- Write I/O ports
-- Write I/O ports

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.