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--===========================================================================--
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--===========================================================================--
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-- --
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-- Synthesizable Hardware Breakpoint Trap --
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-- --
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--===========================================================================--
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--
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--
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-- S Y N T H E Z I A B L E Timer C O R E
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-- File name : trap.vhd
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--
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-- www.OpenCores.Org - May 2003
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-- This core adheres to the GNU public license
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--
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-- File name : Trap.vhd
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--
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--
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-- entity name : trap
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-- Entity name : trap
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--
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--
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-- Purpose : Implements a 8 bit address and data comparitor module
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-- Purpose : Implements a 8 bit address and data hardware breakpoint comparator
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-- which generates an interrupt output on qualified match conditions
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--
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--
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-- Dependencies : ieee.Std_Logic_1164
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-- Dependencies : ieee.Std_Logic_1164
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-- ieee.std_logic_unsigned
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-- ieee.std_logic_unsigned
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--
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--
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-- Author : John E. Kent
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-- Author : John E. Kent
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--
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--
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--===========================================================================----
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-- Email : dilbert57@opencores.org
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--
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-- Revision History:
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--
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--
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-- Date: Revision Author
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-- Web : http://opencores.org/project,system09
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-- 5 May 2003 0.1 John Kent
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--
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--
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--===========================================================================----
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-- Description : Register Memory Map
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--
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--
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-- Register Memory Map
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-- Base + $00 - Address Comparitor High Byte
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-- Base + $01 - Address Comparitor Low byte
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-- Base + $02 - Data Comparitor
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-- Base + $03 - Control Comparitor
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-- Base + $04 - Address Qualifier High Byte
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-- Base + $05 - Address Qualifier Low byte
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-- Base + $06 - Data Qualifier
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-- Base + $07 - Control Qualifier
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--
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-- Address, Data and Control signals
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-- must match in the Comparitor registers
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-- Matches are qualified by setting a bit
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-- in the Qualifier registers
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--
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--
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-- $00 - Address Comparitor High Byte
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-- Control Comparitor / Control Qualify (write)
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-- $01 - Address Comparitor Low byte
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-- $02 - Data Comparitor
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-- $03 - Control Comparitor
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-- $04 - Address Qualifier High Byte
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-- $05 - Address Qualifier Low byte
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-- $06 - Data Qualifier
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-- $07 - Control Qualifier
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--
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-- Address, Data and Control signals must match in the Comparitor registers
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-- Matches are qualified by setting a bit in the Qualifier registers
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--
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-- Control Comparitor / Qualify (write)
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-- b0 - r/w 1=read 0=write
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-- b0 - r/w 1=read 0=write
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-- b1 - vma 1=valid 0=invalid
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-- b1 - vma 1=valid 0=invalid
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-- b7 - irq output 1=match 0=mismatch
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-- b7 - irq output 1=match 0=mismatch
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--
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--
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-- Control Qualifier Read
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-- Control Qualifier Read
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-- b7 - match flag
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-- b7 - match flag
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--
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--
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-- Copyright (C) 2003 - 2010 John Kent
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--===========================================================================--
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-- --
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-- Revision History --
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-- --
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--===========================================================================--
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-- Version Author Date Description
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-- 0.1 John Kent 2003-05-05 Initial version
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-- 0.2 John kent 2010-08-09 Updated header & GPL information
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity trap is
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entity trap is
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((comp_ctrl(0) xor rw ) and qual_ctrl(0) ) or
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((comp_ctrl(0) xor rw ) and qual_ctrl(0) ) or
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((comp_ctrl(1) xor vma ) and qual_ctrl(1) );
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((comp_ctrl(1) xor vma ) and qual_ctrl(1) );
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match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
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match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
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if clk'event and clk = '0' then
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if rst = '1' then
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if rst = '1' then
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match_flag <= '0';
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match_flag <= '0';
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elsif cs = '1' and rw = '0' then
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elsif clk'event and clk = '0' then
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if cs = '1' and rw = '0' then
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match_flag <= '0';
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match_flag <= '0';
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else
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else
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if match = comp_ctrl(7) then
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if match = comp_ctrl(7) then
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match_flag <= '1';
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match_flag <= '1';
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else
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match_flag <= match_flag;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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irq <= match_flag and qual_ctrl(7);
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irq <= match_flag and qual_ctrl(7);
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end process;
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end process;
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