--
-- Flex9 O/S Initialised 8KByte RAM
--
-- v1.0 - 22 December 2006 - John Kent
-- v1.1 -  1 February 2008 - David Burnette
--        reworked to use autogenerated block ram utility

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
	use unisim.vcomponents.all;

entity flex_ram is
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (12 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end flex_ram;

architecture rtl of flex_ram is

  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal cs2    : std_logic;
  signal cs3    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal dp2    : std_logic;
  signal dp3    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
  signal rdata2 : std_logic_vector(7 downto 0);
  signal rdata3 : std_logic_vector(7 downto 0);

component FLEX9_C000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_C800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       data_out : out std_logic_vector (7 downto 0);
       data_in : in  std_logic_vector (7 downto 0)
    );
end component;

begin

   addr_c000 : FLEX9_C000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata0
    );

   addr_c800 : FLEX9_C800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata1
    );
   addr_d000 : FLEX9_D000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs2,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata2
    );
   addr_d800 : FLEX9_D800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs3,
       rw    => rw,
       addr  => addr(10 downto 0),
       data_in => data_in,
       data_out => rdata3
    );

my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
begin
	 we    <= not rw;
	 case addr(12 downto 11) is
	 when "00" =>
		cs0   <= cs;
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= '0';
		data_out <= rdata0;
    when "01" =>
		cs0   <= '0';
		cs1   <= cs;
		cs2   <= '0';
		cs3   <= '0';
		data_out <= rdata1;
	 when "10" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= cs;
		cs3   <= '0';
		data_out <= rdata2;
    when "11" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= cs;
		data_out <= rdata3;
    when others =>
		null;
    end case;		
		
end process;

end architecture rtl;

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