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                               A-Z80
                               A-Z80
             A conceptual implementation of the Z80 CPU
             A conceptual implementation of the Z80 CPU
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             ------------------------------------------
                for Altera, Xilinx and Lattice FPGAs
                for Altera, Xilinx and Lattice FPGAs
 
 
This project is described in more details at www.baltazarstudios.com
This project is described in more details at https://baltazarstudios.com
 
 
For additional information, read 'Quick Start' and 'Users Guide' documents
For additional information, read 'Quick Start' and 'Users Guide' documents
in the 'docs' folder. Also read a 'readme.txt' file in each of the folders.
in the 'docs' folder. Also read a 'readme.txt' file in each of the folders.
 
 
Prerequisites
Prerequisites
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* Python 3.5 or newer
* Python 3.5 or newer
 
 
Importing A-Z80 into your project
Importing A-Z80 into your project
=================================
=================================
If you want to use A-Z80 in your own project, run "export.py" script which
If you want to use A-Z80 in your own project, run "export.py" script which
will copy only files that are needed. Do not manually pick and copy files.
will copy only the files that are needed. Do not manually pick and copy files.
 
 
Folder content
Folder layout
==============
=============
"cpu" folder contains all CPU functional blocks and top-level modules:
"cpu" folder contains CPU functional blocks and all top-level modules:
  alu         ALU block, ALU control and flags logic
  alu         ALU block, ALU control and flags logic
  bus         data bus switches, pin logic, address latch and incrementer
  bus         data bus switches, pin logic, address latch and incrementer
  control     PLA decoder, the sequencer and other control blocks
  control     PLA decoder, the sequencer and other control blocks
  registers   CPU register file and the register control logic
  registers   CPU register file and the register control logic
  toplevel    top level core, interfaces and test code
  toplevel    top level core, interfaces and test code
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  "basic_nexys3" contains the same example project but for Xilinx Nexys3 board
  "basic_nexys3" contains the same example project but for Xilinx Nexys3 board
  "zxspectrum_de1" contains a simple implementation of the Sinclair ZX Spectrum
  "zxspectrum_de1" contains a simple implementation of the Sinclair ZX Spectrum
          for Altera DE1 board
          for Altera DE1 board
 
 
"tools", "resources" contain various tools related to the project; reverse
"tools", "resources" contain various tools related to the project; reverse
  engineering Z80, design verification and testing.
  engineering of the real Z80, design verification and testing.
 
 
Email me if you have any questions, issues or you want to use A-Z80 or any of
Email me if you have any questions, issues or you want to use A-Z80 or any of
the files herein; I'd like to hear from you,
the files within this project. I'd like to hear from you,
 
 
Goran Devic
Goran Devic
gdevic@yahoo.com
gdevic@yahoo.com
 
 
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