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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32.v] - Diff between revs 27 and 32

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Rev 27 Rev 32
Line 39... Line 39...
// Includes
// Includes
//-----------------------------------------------------------------
//-----------------------------------------------------------------
`include "altor32_defs.v"
`include "altor32_defs.v"
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module - AltOR32 CPU
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
//-----------------------------------------------------------------
//-----------------------------------------------------------------
module cpu
module cpu
(
(
    // General
    // General
    input               clk_i /*verilator public*/,
    input               clk_i /*verilator public*/,
Line 54... Line 54...
    output              fault_o /*verilator public*/,
    output              fault_o /*verilator public*/,
    output              break_o /*verilator public*/,
    output              break_o /*verilator public*/,
 
 
    // Instruction memory
    // Instruction memory
    output [31:0]       imem_addr_o /*verilator public*/,
    output [31:0]       imem_addr_o /*verilator public*/,
    output              imem_rd_o /*verilator public*/,
    input [31:0]        imem_dat_i /*verilator public*/,
    output              imem_burst_o /*verilator public*/,
    output [2:0]        imem_cti_o /*verilator public*/,
    input [31:0]        imem_data_in_i /*verilator public*/,
    output              imem_cyc_o /*verilator public*/,
    input               imem_accept_i /*verilator public*/,
    output              imem_stb_o /*verilator public*/,
 
    input               imem_stall_i/*verilator public*/,
    input               imem_ack_i /*verilator public*/,
    input               imem_ack_i /*verilator public*/,
 
 
    // Data memory
    // Data memory
    output [31:0]       dmem_addr_o /*verilator public*/,
    output [31:0]       dmem_addr_o /*verilator public*/,
    output [31:0]       dmem_data_out_o /*verilator public*/,
    output [31:0]       dmem_dat_o /*verilator public*/,
    input [31:0]        dmem_data_in_i /*verilator public*/,
    input [31:0]        dmem_dat_i /*verilator public*/,
    output [3:0]        dmem_wr_o /*verilator public*/,
    output [3:0]        dmem_sel_o /*verilator public*/,
    output              dmem_rd_o /*verilator public*/,
    output [2:0]        dmem_cti_o /*verilator public*/,
    output              dmem_burst_o /*verilator public*/,
    output              dmem_cyc_o /*verilator public*/,
    input               dmem_accept_i /*verilator public*/,
    output              dmem_we_o /*verilator public*/,
 
    output              dmem_stb_o /*verilator public*/,
 
    input               dmem_stall_i/*verilator public*/,
    input               dmem_ack_i /*verilator public*/
    input               dmem_ack_i /*verilator public*/
);
);
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Params
// Params
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wire        icache_invalidate;
wire        icache_invalidate;
 
 
wire [31:0] dcache_addr;
wire [31:0] dcache_addr;
wire [31:0] dcache_data_o;
wire [31:0] dcache_data_o;
wire [31:0] dcache_data_i;
wire [31:0] dcache_data_i;
wire [3:0]  dcache_wr;
wire [3:0]  dcache_sel;
wire        dcache_rd;
wire        dcache_we;
 
wire        dcache_stb;
 
wire        dcache_cyc;
wire        dcache_ack;
wire        dcache_ack;
wire        dcache_accept;
wire        dcache_stall;
wire        dcache_flush;
wire        dcache_flush;
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Instantiation
// Instantiation
//-----------------------------------------------------------------
//-----------------------------------------------------------------
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        // Status
        // Status
        .miss_o(icache_miss),
        .miss_o(icache_miss),
        .busy_o(icache_busy),
        .busy_o(icache_busy),
 
 
        // Instruction memory
        // Instruction memory
        .mem_addr_o(imem_addr_o),
        .wbm_addr_o(imem_addr_o),
        .mem_data_i(imem_data_in_i),
        .wbm_dat_i(imem_dat_i),
        .mem_burst_o(imem_burst_o),
        .wbm_cti_o(imem_cti_o),
        .mem_rd_o(imem_rd_o),
        .wbm_cyc_o(imem_cyc_o),
        .mem_accept_i(imem_accept_i),
        .wbm_stb_o(imem_stb_o),
        .mem_ack_i(imem_ack_i)
        .wbm_stall_i(imem_stall_i),
 
        .wbm_ack_i(imem_ack_i)
    );
    );
end
end
else
else
begin
begin : NO_ICACHE
    // No instruction cache
    // No instruction cache
    altor32_noicache
    altor32_noicache
    u_icache
    u_icache
    (
    (
        .clk_i(clk_i),
        .clk_i(clk_i),
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        .pc_i(icache_pc),
        .pc_i(icache_pc),
        .instruction_o(icache_inst),
        .instruction_o(icache_inst),
        .valid_o(icache_valid),
        .valid_o(icache_valid),
 
 
        // Instruction memory
        // Instruction memory
        .mem_addr_o(imem_addr_o),
        .wbm_addr_o(imem_addr_o),
        .mem_data_i(imem_data_in_i),
        .wbm_dat_i(imem_dat_i),
        .mem_burst_o(imem_burst_o),
        .wbm_cti_o(imem_cti_o),
        .mem_rd_o(imem_rd_o),
        .wbm_cyc_o(imem_cyc_o),
        .mem_accept_i(imem_accept_i),
        .wbm_stb_o(imem_stb_o),
        .mem_ack_i(imem_ack_i)
        .wbm_stall_i(imem_stall_i),
 
        .wbm_ack_i(imem_ack_i)
    );
    );
end
end
endgenerate
endgenerate
 
 
// Instruction Fetch
// Instruction Fetch
Line 244... Line 251...
);
);
 
 
// Register file
// Register file
generate
generate
if (REGISTER_FILE_TYPE == "XILINX")
if (REGISTER_FILE_TYPE == "XILINX")
begin
begin : REGFILE_XIL
    altor32_regfile_xil
    altor32_regfile_xil
    #(
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    )
    reg_bank
    reg_bank
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        .reg_rt_o(w_reg_rb),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
        .reg_rd_i(w_wb_reg_rd)
    );
    );
end
end
else if (REGISTER_FILE_TYPE == "ALTERA")
else if (REGISTER_FILE_TYPE == "ALTERA")
begin
begin : REGFILE_ALT
    altor32_regfile_alt
    altor32_regfile_alt
    #(
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    )
    reg_bank
    reg_bank
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        .reg_rt_o(w_reg_rb),
        .reg_rt_o(w_reg_rb),
        .reg_rd_i(w_wb_reg_rd)
        .reg_rd_i(w_wb_reg_rd)
    );
    );
end
end
else
else
begin
begin : REGFILE_SIM
    altor32_regfile_sim
    altor32_regfile_sim
    #(
    #(
        .SUPPORT_32REGS(SUPPORT_32REGS)
        .SUPPORT_32REGS(SUPPORT_32REGS)
    )
    )
    reg_bank
    reg_bank
Line 313... Line 320...
end
end
endgenerate
endgenerate
 
 
generate
generate
if (ENABLE_DCACHE == "ENABLED")
if (ENABLE_DCACHE == "ENABLED")
begin
begin : DCACHE
    // Data cache
    // Data cache
    altor32_dcache
    altor32_dcache
    u_dcache
    u_dcache
    (
    (
        .clk_i(clk_i),
        .clk_i(clk_i),
Line 327... Line 334...
 
 
        // Processor interface
        // Processor interface
        .address_i({dcache_addr[31:2], 2'b00}),
        .address_i({dcache_addr[31:2], 2'b00}),
        .data_o(dcache_data_i),
        .data_o(dcache_data_i),
        .data_i(dcache_data_o),
        .data_i(dcache_data_o),
        .wr_i(dcache_wr),
        .we_i(dcache_we),
        .rd_i(dcache_rd),
        .stb_i(dcache_stb),
        .accept_o(dcache_accept),
        .sel_i(dcache_sel),
 
        .stall_o(dcache_stall),
        .ack_o(dcache_ack),
        .ack_o(dcache_ack),
 
 
        // Memory interface (slave)
        // Memory interface (slave)
        .mem_addr_o(dmem_addr_o),
        .mem_addr_o(dmem_addr_o),
        .mem_data_i(dmem_data_in_i),
        .mem_data_i(dmem_dat_i),
        .mem_data_o(dmem_data_out_o),
        .mem_data_o(dmem_dat_o),
        .mem_burst_o(dmem_burst_o),
        .mem_sel_o(dmem_sel_o),
        .mem_rd_o(dmem_rd_o),
        .mem_we_o(dmem_we_o),
        .mem_wr_o(dmem_wr_o),
        .mem_stb_o(dmem_stb_o),
        .mem_accept_i(dmem_accept_i),
        .mem_cyc_o(dmem_cyc_o),
 
        .mem_cti_o(dmem_cti_o),
 
        .mem_stall_i(dmem_stall_i),
        .mem_ack_i(dmem_ack_i)
        .mem_ack_i(dmem_ack_i)
    );
    );
end
end
else
else
begin
begin: NO_DCACHE
 
 
    // No data cache
    // No data cache
    assign dmem_addr_o      = {dcache_addr[31:2], 2'b00};
    assign dmem_addr_o      = {dcache_addr[31:2], 2'b00};
    assign dmem_data_out_o  = dcache_data_o;
    assign dmem_dat_o       = dcache_data_o;
    assign dcache_data_i    = dmem_data_in_i;
    assign dcache_data_i    = dmem_dat_i;
    assign dmem_rd_o        = dcache_rd;
    assign dmem_sel_o       = dcache_sel;
    assign dmem_wr_o        = dcache_wr;
    assign dmem_cyc_o       = dcache_cyc;
    assign dmem_burst_o     = 1'b0;
    assign dmem_we_o        = dcache_we;
 
    assign dmem_stb_o       = dcache_stb;
 
    assign dmem_cti_o       = 3'b111;
    assign dcache_ack       = dmem_ack_i;
    assign dcache_ack       = dmem_ack_i;
    assign dcache_accept    = dmem_accept_i;
    assign dcache_stall     = dmem_stall_i;
end
end
endgenerate
endgenerate
 
 
// Execution unit
// Execution unit
altor32_exec
altor32_exec
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    // Memory Interface
    // Memory Interface
    .dmem_addr_o(dcache_addr),
    .dmem_addr_o(dcache_addr),
    .dmem_data_out_o(dcache_data_o),
    .dmem_data_out_o(dcache_data_o),
    .dmem_data_in_i(dcache_data_i),
    .dmem_data_in_i(dcache_data_i),
    .dmem_wr_o(dcache_wr),
    .dmem_sel_o(dcache_sel),
    .dmem_rd_o(dcache_rd),
    .dmem_we_o(dcache_we),
    .dmem_accept_i(dcache_accept),
    .dmem_stb_o(dcache_stb),
 
    .dmem_cyc_o(dcache_cyc),
 
    .dmem_stall_i(dcache_stall),
    .dmem_ack_i(dcache_ack)
    .dmem_ack_i(dcache_ack)
);
);
 
 
// Register file writeback
// Register file writeback
altor32_writeback
altor32_writeback

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