Line 39... |
Line 39... |
// Includes
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// Includes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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`include "altor32_defs.v"
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module - AltOR32 CPU
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// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module cpu
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module cpu
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(
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(
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// General
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// General
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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Line 54... |
Line 54... |
output fault_o /*verilator public*/,
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output fault_o /*verilator public*/,
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output break_o /*verilator public*/,
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output break_o /*verilator public*/,
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// Instruction memory
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// Instruction memory
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output [31:0] imem_addr_o /*verilator public*/,
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output [31:0] imem_addr_o /*verilator public*/,
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output imem_rd_o /*verilator public*/,
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input [31:0] imem_dat_i /*verilator public*/,
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output imem_burst_o /*verilator public*/,
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output [2:0] imem_cti_o /*verilator public*/,
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input [31:0] imem_data_in_i /*verilator public*/,
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output imem_cyc_o /*verilator public*/,
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input imem_accept_i /*verilator public*/,
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output imem_stb_o /*verilator public*/,
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input imem_stall_i/*verilator public*/,
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input imem_ack_i /*verilator public*/,
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input imem_ack_i /*verilator public*/,
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|
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// Data memory
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// Data memory
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output [31:0] dmem_addr_o /*verilator public*/,
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output [31:0] dmem_addr_o /*verilator public*/,
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output [31:0] dmem_data_out_o /*verilator public*/,
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output [31:0] dmem_dat_o /*verilator public*/,
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input [31:0] dmem_data_in_i /*verilator public*/,
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input [31:0] dmem_dat_i /*verilator public*/,
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output [3:0] dmem_wr_o /*verilator public*/,
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output [3:0] dmem_sel_o /*verilator public*/,
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output dmem_rd_o /*verilator public*/,
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output [2:0] dmem_cti_o /*verilator public*/,
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output dmem_burst_o /*verilator public*/,
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output dmem_cyc_o /*verilator public*/,
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input dmem_accept_i /*verilator public*/,
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output dmem_we_o /*verilator public*/,
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output dmem_stb_o /*verilator public*/,
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input dmem_stall_i/*verilator public*/,
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input dmem_ack_i /*verilator public*/
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input dmem_ack_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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Line 138... |
Line 141... |
wire icache_invalidate;
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wire icache_invalidate;
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|
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wire [31:0] dcache_addr;
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wire [31:0] dcache_addr;
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wire [31:0] dcache_data_o;
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wire [31:0] dcache_data_o;
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wire [31:0] dcache_data_i;
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wire [31:0] dcache_data_i;
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wire [3:0] dcache_wr;
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wire [3:0] dcache_sel;
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wire dcache_rd;
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wire dcache_we;
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wire dcache_stb;
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wire dcache_cyc;
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wire dcache_ack;
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wire dcache_ack;
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wire dcache_accept;
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wire dcache_stall;
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wire dcache_flush;
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wire dcache_flush;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Instantiation
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// Instantiation
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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Line 174... |
Line 179... |
// Status
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// Status
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.miss_o(icache_miss),
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.miss_o(icache_miss),
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.busy_o(icache_busy),
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.busy_o(icache_busy),
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// Instruction memory
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// Instruction memory
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.mem_addr_o(imem_addr_o),
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.wbm_addr_o(imem_addr_o),
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.mem_data_i(imem_data_in_i),
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.wbm_dat_i(imem_dat_i),
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.mem_burst_o(imem_burst_o),
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.wbm_cti_o(imem_cti_o),
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.mem_rd_o(imem_rd_o),
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.wbm_cyc_o(imem_cyc_o),
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.mem_accept_i(imem_accept_i),
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.wbm_stb_o(imem_stb_o),
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.mem_ack_i(imem_ack_i)
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.wbm_stall_i(imem_stall_i),
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.wbm_ack_i(imem_ack_i)
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);
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);
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end
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end
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else
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else
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begin
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begin : NO_ICACHE
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// No instruction cache
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// No instruction cache
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altor32_noicache
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altor32_noicache
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u_icache
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u_icache
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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Line 198... |
Line 204... |
.pc_i(icache_pc),
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.pc_i(icache_pc),
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.instruction_o(icache_inst),
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.instruction_o(icache_inst),
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.valid_o(icache_valid),
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.valid_o(icache_valid),
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// Instruction memory
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// Instruction memory
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.mem_addr_o(imem_addr_o),
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.wbm_addr_o(imem_addr_o),
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.mem_data_i(imem_data_in_i),
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.wbm_dat_i(imem_dat_i),
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.mem_burst_o(imem_burst_o),
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.wbm_cti_o(imem_cti_o),
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.mem_rd_o(imem_rd_o),
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.wbm_cyc_o(imem_cyc_o),
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.mem_accept_i(imem_accept_i),
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.wbm_stb_o(imem_stb_o),
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.mem_ack_i(imem_ack_i)
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.wbm_stall_i(imem_stall_i),
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.wbm_ack_i(imem_ack_i)
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);
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);
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end
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end
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endgenerate
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endgenerate
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// Instruction Fetch
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// Instruction Fetch
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Line 244... |
Line 251... |
);
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);
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|
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// Register file
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// Register file
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generate
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generate
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if (REGISTER_FILE_TYPE == "XILINX")
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if (REGISTER_FILE_TYPE == "XILINX")
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begin
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begin : REGFILE_XIL
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altor32_regfile_xil
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altor32_regfile_xil
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#(
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#(
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.SUPPORT_32REGS(SUPPORT_32REGS)
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.SUPPORT_32REGS(SUPPORT_32REGS)
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)
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)
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reg_bank
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reg_bank
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Line 266... |
Line 273... |
.reg_rt_o(w_reg_rb),
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.reg_rt_o(w_reg_rb),
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.reg_rd_i(w_wb_reg_rd)
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.reg_rd_i(w_wb_reg_rd)
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);
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);
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end
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end
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else if (REGISTER_FILE_TYPE == "ALTERA")
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else if (REGISTER_FILE_TYPE == "ALTERA")
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begin
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begin : REGFILE_ALT
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altor32_regfile_alt
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altor32_regfile_alt
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#(
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#(
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.SUPPORT_32REGS(SUPPORT_32REGS)
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.SUPPORT_32REGS(SUPPORT_32REGS)
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)
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)
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reg_bank
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reg_bank
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Line 288... |
Line 295... |
.reg_rt_o(w_reg_rb),
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.reg_rt_o(w_reg_rb),
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.reg_rd_i(w_wb_reg_rd)
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.reg_rd_i(w_wb_reg_rd)
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);
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);
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end
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end
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else
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else
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begin
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begin : REGFILE_SIM
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altor32_regfile_sim
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altor32_regfile_sim
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#(
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#(
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.SUPPORT_32REGS(SUPPORT_32REGS)
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.SUPPORT_32REGS(SUPPORT_32REGS)
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)
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)
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reg_bank
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reg_bank
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Line 313... |
Line 320... |
end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (ENABLE_DCACHE == "ENABLED")
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if (ENABLE_DCACHE == "ENABLED")
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begin
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begin : DCACHE
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// Data cache
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// Data cache
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altor32_dcache
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altor32_dcache
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u_dcache
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u_dcache
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(
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(
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.clk_i(clk_i),
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.clk_i(clk_i),
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Line 327... |
Line 334... |
|
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// Processor interface
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// Processor interface
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.address_i({dcache_addr[31:2], 2'b00}),
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.address_i({dcache_addr[31:2], 2'b00}),
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.data_o(dcache_data_i),
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.data_o(dcache_data_i),
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.data_i(dcache_data_o),
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.data_i(dcache_data_o),
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.wr_i(dcache_wr),
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.we_i(dcache_we),
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.rd_i(dcache_rd),
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.stb_i(dcache_stb),
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.accept_o(dcache_accept),
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.sel_i(dcache_sel),
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.stall_o(dcache_stall),
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.ack_o(dcache_ack),
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.ack_o(dcache_ack),
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// Memory interface (slave)
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// Memory interface (slave)
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.mem_addr_o(dmem_addr_o),
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.mem_addr_o(dmem_addr_o),
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.mem_data_i(dmem_data_in_i),
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.mem_data_i(dmem_dat_i),
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.mem_data_o(dmem_data_out_o),
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.mem_data_o(dmem_dat_o),
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.mem_burst_o(dmem_burst_o),
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.mem_sel_o(dmem_sel_o),
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.mem_rd_o(dmem_rd_o),
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.mem_we_o(dmem_we_o),
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.mem_wr_o(dmem_wr_o),
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.mem_stb_o(dmem_stb_o),
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.mem_accept_i(dmem_accept_i),
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.mem_cyc_o(dmem_cyc_o),
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.mem_cti_o(dmem_cti_o),
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.mem_stall_i(dmem_stall_i),
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.mem_ack_i(dmem_ack_i)
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.mem_ack_i(dmem_ack_i)
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);
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);
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end
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end
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else
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else
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begin
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begin: NO_DCACHE
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|
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// No data cache
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// No data cache
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assign dmem_addr_o = {dcache_addr[31:2], 2'b00};
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assign dmem_addr_o = {dcache_addr[31:2], 2'b00};
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assign dmem_data_out_o = dcache_data_o;
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assign dmem_dat_o = dcache_data_o;
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assign dcache_data_i = dmem_data_in_i;
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assign dcache_data_i = dmem_dat_i;
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assign dmem_rd_o = dcache_rd;
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assign dmem_sel_o = dcache_sel;
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assign dmem_wr_o = dcache_wr;
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assign dmem_cyc_o = dcache_cyc;
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assign dmem_burst_o = 1'b0;
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assign dmem_we_o = dcache_we;
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assign dmem_stb_o = dcache_stb;
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assign dmem_cti_o = 3'b111;
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assign dcache_ack = dmem_ack_i;
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assign dcache_ack = dmem_ack_i;
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assign dcache_accept = dmem_accept_i;
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assign dcache_stall = dmem_stall_i;
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end
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end
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endgenerate
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endgenerate
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// Execution unit
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// Execution unit
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altor32_exec
|
altor32_exec
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Line 414... |
Line 426... |
|
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// Memory Interface
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// Memory Interface
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.dmem_addr_o(dcache_addr),
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.dmem_addr_o(dcache_addr),
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.dmem_data_out_o(dcache_data_o),
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.dmem_data_out_o(dcache_data_o),
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.dmem_data_in_i(dcache_data_i),
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.dmem_data_in_i(dcache_data_i),
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.dmem_wr_o(dcache_wr),
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.dmem_sel_o(dcache_sel),
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.dmem_rd_o(dcache_rd),
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.dmem_we_o(dcache_we),
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.dmem_accept_i(dcache_accept),
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.dmem_stb_o(dcache_stb),
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.dmem_cyc_o(dcache_cyc),
|
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.dmem_stall_i(dcache_stall),
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.dmem_ack_i(dcache_ack)
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.dmem_ack_i(dcache_ack)
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);
|
);
|
|
|
// Register file writeback
|
// Register file writeback
|
altor32_writeback
|
altor32_writeback
|