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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter ISR_VECTOR = 32'h00000000;
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parameter ISR_VECTOR = 32'h00000000;
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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parameter ENABLE_ICACHE = "ENABLED";
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parameter ENABLE_ICACHE = "ENABLED";
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parameter ENABLE_DCACHE = "DISABLED";
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parameter ENABLE_DCACHE = "DISABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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parameter PIPELINED_FETCH = "ENABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers / Wires
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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wire w_e_stall;
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wire w_e_stall;
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wire icache_rd;
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wire icache_rd;
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wire [31:0] icache_pc;
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wire [31:0] icache_pc;
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wire [31:0] icache_inst;
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wire [31:0] icache_inst;
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wire icache_miss;
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wire icache_valid;
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wire icache_valid;
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wire icache_busy;
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wire icache_invalidate;
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wire icache_invalidate;
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wire [31:0] dcache_addr;
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wire [31:0] dcache_addr;
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wire [31:0] dcache_data_o;
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wire [31:0] dcache_data_o;
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wire [31:0] dcache_data_i;
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wire [31:0] dcache_data_i;
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.pc_i(icache_pc),
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.pc_i(icache_pc),
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.instruction_o(icache_inst),
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.instruction_o(icache_inst),
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.valid_o(icache_valid),
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.valid_o(icache_valid),
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.invalidate_i(icache_invalidate),
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.invalidate_i(icache_invalidate),
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// Status
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.miss_o(icache_miss),
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.busy_o(icache_busy),
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// Instruction memory
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// Instruction memory
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.wbm_addr_o(imem_addr_o),
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.wbm_addr_o(imem_addr_o),
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.wbm_dat_i(imem_dat_i),
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.wbm_dat_i(imem_dat_i),
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.wbm_cti_o(imem_cti_o),
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.wbm_cti_o(imem_cti_o),
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.wbm_cyc_o(imem_cyc_o),
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.wbm_cyc_o(imem_cyc_o),
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// Processor interface
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// Processor interface
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.rd_i(icache_rd),
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.rd_i(icache_rd),
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.pc_i(icache_pc),
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.pc_i(icache_pc),
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.instruction_o(icache_inst),
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.instruction_o(icache_inst),
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.valid_o(icache_valid),
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.valid_o(icache_valid),
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.invalidate_i(icache_invalidate),
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// Instruction memory
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// Instruction memory
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.wbm_addr_o(imem_addr_o),
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.wbm_addr_o(imem_addr_o),
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.wbm_dat_i(imem_dat_i),
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.wbm_dat_i(imem_dat_i),
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.wbm_cti_o(imem_cti_o),
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.wbm_cti_o(imem_cti_o),
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endgenerate
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endgenerate
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// Instruction Fetch
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// Instruction Fetch
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altor32_fetch
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altor32_fetch
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#(
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#(
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.BOOT_VECTOR(BOOT_VECTOR)
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.BOOT_VECTOR(BOOT_VECTOR),
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.PIPELINED_FETCH(PIPELINED_FETCH)
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)
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)
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u_fetch
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u_fetch
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(
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(
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// General
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// General
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.clk_i(clk_i),
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.clk_i(clk_i),
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.mem_ack_i(dmem_ack_i)
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.mem_ack_i(dmem_ack_i)
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);
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);
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end
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end
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else
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else
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begin: NO_DCACHE
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begin: NO_DCACHE
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// No data cache
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// No data cache
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assign dmem_addr_o = {dcache_addr[31:2], 2'b00};
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assign dmem_addr_o = {dcache_addr[31:2], 2'b00};
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assign dmem_dat_o = dcache_data_o;
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assign dmem_dat_o = dcache_data_o;
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assign dcache_data_i = dmem_dat_i;
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assign dcache_data_i = dmem_dat_i;
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assign dmem_sel_o = dcache_sel;
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assign dmem_sel_o = dcache_sel;
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