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Line 8... |
// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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| Line 71... |
Line 71... |
`include "altor32_funcs.v"
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`include "altor32_funcs.v"
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [31:0] result;
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reg [31:0] result_r;
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reg [31:16] shift_right_fill;
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reg [31:16] shift_right_fill_r;
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reg [31:0] shift_right_1;
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reg [31:0] shift_right_1_r;
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reg [31:0] shift_right_2;
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reg [31:0] shift_right_2_r;
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reg [31:0] shift_right_4;
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reg [31:0] shift_right_4_r;
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reg [31:0] shift_right_8;
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reg [31:0] shift_right_8_r;
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reg [31:0] shift_left_1;
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reg [31:0] shift_left_1_r;
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reg [31:0] shift_left_2;
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reg [31:0] shift_left_2_r;
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reg [31:0] shift_left_4;
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reg [31:0] shift_left_4_r;
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reg [31:0] shift_left_8;
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reg [31:0] shift_left_8_r;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// ALU
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// ALU
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (op_i or a_i or b_i or c_i)
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always @ (op_i or a_i or b_i or c_i)
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Line 96... |
// Shift Left
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// Shift Left
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//----------------------------------------------
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//----------------------------------------------
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`ALU_SHIFTL :
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`ALU_SHIFTL :
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begin
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begin
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if (b_i[0] == 1'b1)
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if (b_i[0] == 1'b1)
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shift_left_1 = {a_i[30:0],1'b0};
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shift_left_1_r = {a_i[30:0],1'b0};
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else
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else
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shift_left_1 = a_i;
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shift_left_1_r = a_i;
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if (b_i[1] == 1'b1)
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if (b_i[1] == 1'b1)
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shift_left_2 = {shift_left_1[29:0],2'b00};
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shift_left_2_r = {shift_left_1_r[29:0],2'b00};
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else
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else
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shift_left_2 = shift_left_1;
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shift_left_2_r = shift_left_1_r;
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if (b_i[2] == 1'b1)
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if (b_i[2] == 1'b1)
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shift_left_4 = {shift_left_2[27:0],4'b0000};
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shift_left_4_r = {shift_left_2_r[27:0],4'b0000};
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else
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else
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shift_left_4 = shift_left_2;
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shift_left_4_r = shift_left_2_r;
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if (b_i[3] == 1'b1)
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if (b_i[3] == 1'b1)
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shift_left_8 = {shift_left_4[23:0],8'b00000000};
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shift_left_8_r = {shift_left_4_r[23:0],8'b00000000};
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else
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else
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shift_left_8 = shift_left_4;
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shift_left_8_r = shift_left_4_r;
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if (b_i[4] == 1'b1)
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if (b_i[4] == 1'b1)
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result = {shift_left_8[15:0],16'b0000000000000000};
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result_r = {shift_left_8_r[15:0],16'b0000000000000000};
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else
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else
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result = shift_left_8;
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result_r = shift_left_8_r;
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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//----------------------------------------------
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//----------------------------------------------
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| Line 130... |
Line 130... |
//----------------------------------------------
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//----------------------------------------------
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`ALU_SHIFTR, `ALU_SHIRTR_ARITH:
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`ALU_SHIFTR, `ALU_SHIRTR_ARITH:
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begin
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begin
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// Arithmetic shift? Fill with 1's if MSB set
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// Arithmetic shift? Fill with 1's if MSB set
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if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH)
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if (a_i[31] == 1'b1 && op_i == `ALU_SHIRTR_ARITH)
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shift_right_fill = 16'b1111111111111111;
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shift_right_fill_r = 16'b1111111111111111;
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else
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else
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shift_right_fill = 16'b0000000000000000;
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shift_right_fill_r = 16'b0000000000000000;
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if (b_i[0] == 1'b1)
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if (b_i[0] == 1'b1)
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shift_right_1 = {shift_right_fill[31], a_i[31:1]};
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shift_right_1_r = {shift_right_fill_r[31], a_i[31:1]};
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else
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else
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shift_right_1 = a_i;
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shift_right_1_r = a_i;
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if (b_i[1] == 1'b1)
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if (b_i[1] == 1'b1)
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shift_right_2 = {shift_right_fill[31:30], shift_right_1[31:2]};
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shift_right_2_r = {shift_right_fill_r[31:30], shift_right_1_r[31:2]};
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else
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else
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shift_right_2 = shift_right_1;
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shift_right_2_r = shift_right_1_r;
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if (b_i[2] == 1'b1)
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if (b_i[2] == 1'b1)
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shift_right_4 = {shift_right_fill[31:28], shift_right_2[31:4]};
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shift_right_4_r = {shift_right_fill_r[31:28], shift_right_2_r[31:4]};
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else
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else
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shift_right_4 = shift_right_2;
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shift_right_4_r = shift_right_2_r;
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if (b_i[3] == 1'b1)
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if (b_i[3] == 1'b1)
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shift_right_8 = {shift_right_fill[31:24], shift_right_4[31:8]};
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shift_right_8_r = {shift_right_fill_r[31:24], shift_right_4_r[31:8]};
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else
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else
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shift_right_8 = shift_right_4;
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shift_right_8_r = shift_right_4_r;
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if (b_i[4] == 1'b1)
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if (b_i[4] == 1'b1)
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result = {shift_right_fill[31:16], shift_right_8[31:16]};
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result_r = {shift_right_fill_r[31:16], shift_right_8_r[31:16]};
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else
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else
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result = shift_right_8;
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result_r = shift_right_8_r;
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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//----------------------------------------------
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//----------------------------------------------
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// Arithmetic
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// Arithmetic
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//----------------------------------------------
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//----------------------------------------------
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`ALU_ADD :
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`ALU_ADD :
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begin
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begin
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{c_o, result} = (a_i + b_i);
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{c_o, result_r} = (a_i + b_i);
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c_update_o = 1'b1;
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c_update_o = 1'b1;
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end
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end
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`ALU_ADDC :
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`ALU_ADDC :
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begin
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begin
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{c_o, result} = (a_i + b_i) + {31'h00000000, c_i};
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{c_o, result_r} = (a_i + b_i) + {31'h00000000, c_i};
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c_update_o = 1'b1;
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c_update_o = 1'b1;
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end
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end
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`ALU_SUB :
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`ALU_SUB :
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begin
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begin
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result = (a_i - b_i);
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result_r = (a_i - b_i);
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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//----------------------------------------------
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//----------------------------------------------
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// Logical
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// Logical
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//----------------------------------------------
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//----------------------------------------------
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`ALU_AND :
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`ALU_AND :
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begin
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begin
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result = (a_i & b_i);
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result_r = (a_i & b_i);
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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`ALU_OR :
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`ALU_OR :
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begin
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begin
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result = (a_i | b_i);
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result_r = (a_i | b_i);
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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`ALU_XOR :
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`ALU_XOR :
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begin
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begin
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result = (a_i ^ b_i);
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result_r = (a_i ^ b_i);
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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default :
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default :
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begin
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begin
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result = a_i;
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result_r = a_i;
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c_o = 1'b0;
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c_o = 1'b0;
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c_update_o = 1'b0;
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c_update_o = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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|
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assign p_o = result;
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assign p_o = result_r;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Comparisons
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// Comparisons
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
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always @ *
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always @ *
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