| Line 62... |
Line 62... |
|
|
// Memory interface (slave)
|
// Memory interface (slave)
|
output reg [31:0] mem_addr_o /*verilator public*/,
|
output reg [31:0] mem_addr_o /*verilator public*/,
|
input [31:0] mem_data_i /*verilator public*/,
|
input [31:0] mem_data_i /*verilator public*/,
|
output reg [31:0] mem_data_o /*verilator public*/,
|
output reg [31:0] mem_data_o /*verilator public*/,
|
output reg mem_burst_o /*verilator public*/,
|
output reg [2:0] mem_cti_o /*verilator public*/,
|
output reg mem_rd_o /*verilator public*/,
|
output reg mem_cyc_o /*verilator public*/,
|
output reg [3:0] mem_wr_o /*verilator public*/,
|
output reg mem_stb_o /*verilator public*/,
|
input mem_accept_i/*verilator public*/,
|
output reg mem_we_o /*verilator public*/,
|
|
output reg [3:0] mem_sel_o /*verilator public*/,
|
|
input mem_stall_i/*verilator public*/,
|
input mem_ack_i/*verilator public*/
|
input mem_ack_i/*verilator public*/
|
);
|
);
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Params
|
// Params
|
| Line 80... |
Line 82... |
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Registers / Wires
|
// Registers / Wires
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
|
|
reg [31:CACHE_LINE_SIZE_WIDTH] line_address;
|
reg [31:CACHE_LINE_SIZE_WIDTH] line_address;
|
reg [CACHE_LINE_SIZE_WIDTH-3:0] line_word;
|
|
|
reg [CACHE_LINE_WORDS_IDX_MAX-1:0] response_idx;
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|
|
|
reg [CACHE_LINE_WORDS_IDX_MAX-1:0] request_idx;
|
|
wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_request_idx = request_idx + 1'b1;
|
|
|
|
reg [CACHE_LINE_WORDS_IDX_MAX-1:0] cache_idx;
|
|
wire [CACHE_LINE_WORDS_IDX_MAX-1:0] next_cache_idx = cache_idx + 1'b1;
|
|
|
|
|
// Current state
|
// Current state
|
parameter STATE_IDLE = 0;
|
parameter STATE_IDLE = 0;
|
parameter STATE_FETCH = 1;
|
parameter STATE_FETCH = 1;
|
parameter STATE_READ_WAIT = 2;
|
parameter STATE_WRITE_SETUP = 2;
|
parameter STATE_WRITE = 3;
|
parameter STATE_WRITE = 3;
|
parameter STATE_WRITE_WAIT = 4;
|
parameter STATE_WRITE_WAIT = 4;
|
parameter STATE_READ_SINGLE = 5;
|
parameter STATE_MEM_SINGLE = 5;
|
parameter STATE_WRITE_SINGLE= 6;
|
parameter STATE_FETCH_WAIT = 6;
|
|
|
reg [3:0] state;
|
reg [3:0] state;
|
|
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
// Control logic
|
// Next State Logic
|
//-----------------------------------------------------------------
|
//-----------------------------------------------------------------
|
reg [CACHE_LINE_SIZE_WIDTH-3:0] v_line_word;
|
reg [3:0] next_state_r;
|
|
always @ *
|
|
begin
|
|
next_state_r = state;
|
|
|
|
case (state)
|
|
//-----------------------------------------
|
|
// IDLE
|
|
//-----------------------------------------
|
|
STATE_IDLE :
|
|
begin
|
|
// Perform cache evict (write)
|
|
if (evict_i)
|
|
next_state_r = STATE_WRITE_SETUP;
|
|
// Perform cache fill (read)
|
|
else if (fill_i)
|
|
next_state_r = STATE_FETCH;
|
|
// Read/Write single
|
|
else if (rd_single_i | (|wr_single_i))
|
|
next_state_r = STATE_MEM_SINGLE;
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH - Fetch line from memory
|
|
//-----------------------------------------
|
|
STATE_FETCH :
|
|
begin
|
|
// Line fetch complete?
|
|
if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
next_state_r = STATE_FETCH_WAIT;
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH_WAIT - Wait for read responses
|
|
//-----------------------------------------
|
|
STATE_FETCH_WAIT:
|
|
begin
|
|
// Read from memory complete
|
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
next_state_r = STATE_IDLE;
|
|
end
|
|
//-----------------------------------------
|
|
// WRITE_SETUP - Wait for data from cache
|
|
//-----------------------------------------
|
|
STATE_WRITE_SETUP :
|
|
next_state_r = STATE_WRITE;
|
|
//-----------------------------------------
|
|
// WRITE - Write word to memory
|
|
//-----------------------------------------
|
|
STATE_WRITE :
|
|
begin
|
|
// Line write complete?
|
|
if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
next_state_r = STATE_WRITE_WAIT;
|
|
// Fetch next word for line
|
|
else if (~mem_stall_i | ~mem_stb_o)
|
|
next_state_r = STATE_WRITE_SETUP;
|
|
end
|
|
//-----------------------------------------
|
|
// WRITE_WAIT - Wait for write to complete
|
|
//-----------------------------------------
|
|
STATE_WRITE_WAIT:
|
|
begin
|
|
// Write to memory complete
|
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
next_state_r = STATE_IDLE;
|
|
end
|
|
//-----------------------------------------
|
|
// MEM_SINGLE - Single access to memory
|
|
//-----------------------------------------
|
|
STATE_MEM_SINGLE:
|
|
begin
|
|
// Data ready from memory?
|
|
if (mem_ack_i)
|
|
next_state_r = STATE_IDLE;
|
|
end
|
|
default:
|
|
;
|
|
endcase
|
|
end
|
|
|
|
// Update state
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
state <= STATE_IDLE;
|
|
else
|
|
state <= next_state_r;
|
|
end
|
|
|
|
//-----------------------------------------------------------------
|
|
// Control logic
|
|
//-----------------------------------------------------------------
|
always @ (posedge rst_i or posedge clk_i )
|
always @ (posedge rst_i or posedge clk_i )
|
begin
|
begin
|
if (rst_i == 1'b1)
|
if (rst_i == 1'b1)
|
begin
|
begin
|
line_address <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
|
line_address <= {32-CACHE_LINE_SIZE_WIDTH{1'b0}};
|
line_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
mem_addr_o <= 32'h00000000;
|
|
mem_data_o <= 32'h00000000;
|
|
mem_wr_o <= 4'h0;
|
|
mem_rd_o <= 1'b0;
|
|
mem_burst_o <= 1'b0;
|
|
cache_addr_o <= 30'h00000000;
|
|
cache_data_o <= 32'h00000000;
|
|
cache_wr_o <= 1'b0;
|
|
done_o <= 1'b0;
|
done_o <= 1'b0;
|
data_o <= 32'h00000000;
|
data_o <= 32'h00000000;
|
state <= STATE_IDLE;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
done_o <= 1'b0;
|
|
|
|
case (state)
|
|
|
if (mem_accept_i)
|
//-----------------------------------------
|
|
// IDLE
|
|
//-----------------------------------------
|
|
STATE_IDLE :
|
begin
|
begin
|
mem_rd_o <= 1'b0;
|
// Perform cache evict (write)
|
mem_wr_o <= 4'h0;
|
if (evict_i)
|
|
line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
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// Perform cache fill (read)
|
|
else if (fill_i)
|
|
line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH/WRITE_WAIT - Wait for oustanding responses
|
|
//-----------------------------------------
|
|
STATE_WRITE_WAIT,
|
|
STATE_FETCH_WAIT:
|
|
begin
|
|
// Write to memory complete
|
|
if (mem_ack_i)
|
|
begin
|
|
// Line write complete?
|
|
if (response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
done_o <= 1'b1;
|
|
end
|
|
end
|
|
//-----------------------------------------
|
|
// MEM_SINGLE - Single access to memory
|
|
//-----------------------------------------
|
|
STATE_MEM_SINGLE:
|
|
begin
|
|
// Data ready from memory?
|
|
if (mem_ack_i)
|
|
begin
|
|
data_o <= mem_data_i;
|
|
done_o <= 1'b1;
|
|
end
|
|
end
|
|
default:
|
|
;
|
|
endcase
|
|
end
|
end
|
end
|
|
|
done_o <= 1'b0;
|
//-----------------------------------------------------------------
|
|
// Cache Read / Write
|
|
//-----------------------------------------------------------------
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
begin
|
|
cache_addr_o <= 30'h00000000;
|
|
cache_data_o <= 32'h00000000;
|
|
cache_wr_o <= 1'b0;
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|
|
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
end
|
|
else
|
|
begin
|
cache_wr_o <= 1'b0;
|
cache_wr_o <= 1'b0;
|
|
|
case (state)
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// IDLE
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_IDLE :
|
STATE_IDLE :
|
begin
|
begin
|
|
cache_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
|
// Perform cache evict (write)
|
// Perform cache evict (write)
|
if (evict_i)
|
if (evict_i)
|
begin
|
begin
|
line_address <= evict_addr_i[31:CACHE_LINE_SIZE_WIDTH];
|
|
line_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
|
|
// Read data from cache
|
// Read data from cache
|
cache_addr_o <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH-2{1'b0}}};
|
cache_addr_o <= {evict_addr_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_WORDS_IDX_MAX{1'b0}}};
|
state <= STATE_READ_WAIT;
|
end
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH - Fetch line from memory
|
|
//-----------------------------------------
|
|
STATE_FETCH,
|
|
STATE_FETCH_WAIT:
|
|
begin
|
|
// Data ready from memory?
|
|
if (mem_ack_i)
|
|
begin
|
|
// Write data into cache
|
|
cache_addr_o <= {line_address, cache_idx};
|
|
cache_data_o <= mem_data_i;
|
|
cache_wr_o <= 1'b1;
|
|
|
|
cache_idx <= next_cache_idx;
|
|
end
|
|
end
|
|
//-----------------------------------------
|
|
// WRITE - Write word to memory
|
|
//-----------------------------------------
|
|
STATE_WRITE_SETUP:
|
|
begin
|
|
|
|
end
|
|
STATE_WRITE,
|
|
STATE_WRITE_WAIT:
|
|
begin
|
|
if (~mem_stall_i | ~mem_stb_o)
|
|
begin
|
|
// Setup next word read from cache
|
|
cache_addr_o <= {line_address, next_cache_idx};
|
|
cache_idx <= next_cache_idx;
|
|
end
|
|
end
|
|
default:
|
|
;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
//-----------------------------------------------------------------
|
|
// Request
|
|
//-----------------------------------------------------------------
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
begin
|
|
mem_addr_o <= 32'h00000000;
|
|
mem_data_o <= 32'h00000000;
|
|
mem_sel_o <= 4'h0;
|
|
mem_cti_o <= 3'b0;
|
|
mem_stb_o <= 1'b0;
|
|
mem_we_o <= 1'b0;
|
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
end
|
|
else
|
|
begin
|
|
if (~mem_stall_i)
|
|
begin
|
|
mem_stb_o <= 1'b0;
|
|
|
|
// TMP
|
|
if (mem_cti_o == 3'b111)
|
|
begin
|
|
//mem_addr_o <= 32'h00000000;
|
|
mem_data_o <= 32'h00000000;
|
|
mem_sel_o <= 4'h0;
|
|
mem_cti_o <= 3'b0;
|
|
mem_stb_o <= 1'b0;
|
|
mem_we_o <= 1'b0;
|
|
end
|
|
end
|
|
|
|
case (state)
|
|
|
|
//-----------------------------------------
|
|
// IDLE
|
|
//-----------------------------------------
|
|
STATE_IDLE :
|
|
begin
|
|
request_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
|
|
// Perform cache evict (write)
|
|
if (evict_i)
|
|
begin
|
|
|
end
|
end
|
// Perform cache fill (read)
|
// Perform cache fill (read)
|
else if (fill_i)
|
else if (fill_i)
|
begin
|
begin
|
line_address <= address_i[31:CACHE_LINE_SIZE_WIDTH];
|
|
line_word <= {CACHE_LINE_SIZE_WIDTH-2{1'b0}};
|
|
|
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
mem_addr_o <= {address_i[31:CACHE_LINE_SIZE_WIDTH], {CACHE_LINE_SIZE_WIDTH{1'b0}}};
|
mem_rd_o <= 1'b1;
|
mem_data_o <= 32'h00000000;
|
mem_burst_o <= 1'b1;
|
mem_sel_o <= 4'b1111;
|
state <= STATE_FETCH;
|
mem_cti_o <= 3'b010;
|
|
mem_stb_o <= 1'b1;
|
|
mem_we_o <= 1'b0;
|
|
|
|
request_idx <= next_request_idx;
|
end
|
end
|
// Read single
|
// Read single
|
else if (rd_single_i)
|
else if (rd_single_i)
|
begin
|
begin
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= address_i;
|
mem_addr_o <= address_i;
|
mem_data_o <= 32'b0;
|
mem_data_o <= 32'h00000000;
|
mem_rd_o <= 1'b1;
|
mem_sel_o <= 4'b1111;
|
mem_burst_o <= 1'b0;
|
mem_cti_o <= 3'b111;
|
state <= STATE_READ_SINGLE;
|
mem_stb_o <= 1'b1;
|
|
mem_we_o <= 1'b0;
|
end
|
end
|
// Write single
|
// Write single
|
else if (|wr_single_i)
|
else if (|wr_single_i)
|
begin
|
begin
|
// Start fetch from memory
|
// Start fetch from memory
|
mem_addr_o <= address_i;
|
mem_addr_o <= address_i;
|
mem_data_o <= data_i;
|
mem_data_o <= data_i;
|
mem_wr_o <= wr_single_i;
|
mem_sel_o <= wr_single_i;
|
mem_burst_o <= 1'b0;
|
mem_cti_o <= 3'b111;
|
state <= STATE_WRITE_SINGLE;
|
mem_stb_o <= 1'b1;
|
|
mem_we_o <= 1'b1;
|
end
|
end
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// FETCH - Fetch line from memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_FETCH :
|
STATE_FETCH :
|
begin
|
begin
|
// Data ready from memory?
|
// Previous request accepted?
|
if (mem_ack_i && mem_rd_o == 1'b0)
|
if (~mem_stall_i)
|
begin
|
begin
|
// Write data into cache
|
// Fetch next word for line
|
cache_addr_o <= {line_address, line_word};
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
cache_data_o <= mem_data_i;
|
mem_stb_o <= 1'b1;
|
cache_wr_o <= 1'b1;
|
|
|
|
// Line fetch complete?
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
if (line_word == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_cti_o <= 3'b111;
|
begin
|
|
done_o <= 1'b1;
|
request_idx <= next_request_idx;
|
state <= STATE_IDLE;
|
|
end
|
end
|
// Fetch next word for line
|
end
|
else
|
//-----------------------------------------
|
|
// WRITE - Write word to memory
|
|
//-----------------------------------------
|
|
STATE_WRITE :
|
begin
|
begin
|
v_line_word = line_word + 1'b1;
|
// Memory interface can request command?
|
line_word <= v_line_word;
|
if (~mem_stall_i | ~mem_stb_o)
|
|
begin
|
|
// Write data into memory from cache
|
|
mem_addr_o <= {line_address, request_idx, 2'b00};
|
|
mem_data_o <= cache_data_i;
|
|
mem_sel_o <= 4'b1111;
|
|
mem_stb_o <= 1'b1;
|
|
mem_we_o <= 1'b1;
|
|
|
mem_addr_o <= {line_address, v_line_word, 2'b00};
|
if (request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
mem_rd_o <= 1'b1;
|
mem_cti_o <= 3'b111;
|
|
else
|
|
mem_cti_o <= 3'b010;
|
|
|
if (line_word == ({CACHE_LINE_WORDS_IDX_MAX{1'b1}}-1))
|
request_idx <= next_request_idx;
|
begin
|
|
mem_burst_o <= 1'b0;
|
|
end
|
end
|
end
|
end
|
|
default:
|
|
;
|
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
//-----------------------------------------------------------------
|
|
// Memory Response Counter
|
|
//-----------------------------------------------------------------
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
|
else
|
|
begin
|
|
case (state)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// READ_WAIT - Wait for data from cache
|
// IDLE
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_READ_WAIT :
|
STATE_IDLE :
|
begin
|
begin
|
// Not used yet, but set for start of burst
|
response_idx <= {CACHE_LINE_WORDS_IDX_MAX{1'b0}};
|
mem_burst_o <= 1'b1;
|
|
state <= STATE_WRITE;
|
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE - Write word to memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE :
|
STATE_FETCH,
|
|
STATE_FETCH_WAIT :
|
begin
|
begin
|
// Write data into memory from cache
|
// Data ready from memory?
|
mem_addr_o <= {line_address, line_word, 2'b00};
|
if (mem_ack_i)
|
mem_data_o <= cache_data_i;
|
response_idx <= response_idx + 1'b1;
|
mem_wr_o <= 4'b1111;
|
|
|
|
// Setup next word read from cache
|
|
v_line_word = line_word + 1'b1;
|
|
cache_addr_o <= {line_address, v_line_word};
|
|
|
|
state <= STATE_WRITE_WAIT;
|
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE_WAIT - Wait for write to complete
|
// WRITE_WAIT - Wait for write to complete
|
//-----------------------------------------
|
//-----------------------------------------
|
|
STATE_WRITE,
|
|
STATE_WRITE_SETUP,
|
STATE_WRITE_WAIT:
|
STATE_WRITE_WAIT:
|
begin
|
begin
|
// Write to memory complete
|
// Write to memory complete
|
if (mem_ack_i && mem_wr_o == 4'b0)
|
if (mem_ack_i)
|
begin
|
response_idx <= response_idx + 1'b1;
|
// Line write complete?
|
|
if (line_word == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
begin
|
|
done_o <= 1'b1;
|
|
state <= STATE_IDLE;
|
|
end
|
end
|
// Fetch next word for line
|
default:
|
|
;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
//-----------------------------------------------------------------
|
|
// CYC_O
|
|
//-----------------------------------------------------------------
|
|
always @ (posedge rst_i or posedge clk_i )
|
|
begin
|
|
if (rst_i == 1'b1)
|
|
mem_cyc_o <= 1'b0;
|
else
|
else
|
begin
|
begin
|
line_word <= line_word + 1'b1;
|
case (state)
|
state <= STATE_WRITE;
|
|
|
//-----------------------------------------
|
|
// IDLE
|
|
//-----------------------------------------
|
|
STATE_IDLE :
|
|
begin
|
|
// Perform cache evict (write)
|
|
if (evict_i)
|
|
begin
|
|
|
if (line_word == ({CACHE_LINE_WORDS_IDX_MAX{1'b1}}-1))
|
|
mem_burst_o <= 1'b0;
|
|
end
|
|
end
|
end
|
|
// Perform cache fill (read)
|
|
else if (fill_i)
|
|
mem_cyc_o <= 1'b1;
|
|
// Read single
|
|
else if (rd_single_i)
|
|
mem_cyc_o <= 1'b1;
|
|
// Write single
|
|
else if (|wr_single_i)
|
|
mem_cyc_o <= 1'b1;
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// READ_SINGLE - Single access to memory
|
// FETCH - Fetch line from memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_READ_SINGLE:
|
STATE_FETCH :
|
begin
|
begin
|
// Data ready from memory?
|
// Data ready from memory?
|
if (mem_ack_i && mem_rd_o == 1'b0)
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
begin
|
mem_cyc_o <= 1'b0;
|
data_o <= mem_data_i;
|
|
done_o <= 1'b1;
|
|
state <= STATE_IDLE;
|
|
end
|
|
end
|
end
|
//-----------------------------------------
|
//-----------------------------------------
|
// WRITE_SINGLE - Single access to memory
|
// WRITE - Write word to memory
|
//-----------------------------------------
|
//-----------------------------------------
|
STATE_WRITE_SINGLE:
|
STATE_WRITE :
|
begin
|
begin
|
if (mem_ack_i && mem_wr_o == 4'b0)
|
// Write data into memory from cache
|
|
mem_cyc_o <= 1'b1;
|
|
end
|
|
//-----------------------------------------
|
|
// FETCH/WRITE_WAIT - Wait for responses
|
|
//-----------------------------------------
|
|
STATE_WRITE_WAIT,
|
|
STATE_FETCH_WAIT:
|
begin
|
begin
|
done_o <= 1'b1;
|
// Write to memory complete
|
state <= STATE_IDLE;
|
if (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})
|
|
mem_cyc_o <= 1'b0;
|
end
|
end
|
|
//-----------------------------------------
|
|
// MEM_SINGLE - Single access to memory
|
|
//-----------------------------------------
|
|
STATE_MEM_SINGLE:
|
|
begin
|
|
// Data ready from memory?
|
|
if (mem_ack_i)
|
|
mem_cyc_o <= 1'b0;
|
end
|
end
|
default:
|
default:
|
;
|
;
|
endcase
|
endcase
|
end
|
end
|
