| Line 34... |
Line 34... |
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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|
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//`define CONF_CORE_DEBUG
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//`define CONF_CORE_DEBUG
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//`define CONF_CORE_DEBUG_BUBBLE
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//`define CONF_CORE_TRACE
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//`define CONF_CORE_TRACE
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//`define CONF_CORE_FAULT_ON_OPCODE0
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Includes
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// Includes
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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`include "altor32_defs.v"
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`include "altor32_defs.v"
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| Line 104... |
Line 102... |
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// Memory Interface
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// Memory Interface
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output reg [31:0] dmem_addr_o /*verilator public*/,
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output reg [31:0] dmem_addr_o /*verilator public*/,
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output reg [31:0] dmem_data_out_o /*verilator public*/,
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output reg [31:0] dmem_data_out_o /*verilator public*/,
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input [31:0] dmem_data_in_i /*verilator public*/,
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input [31:0] dmem_data_in_i /*verilator public*/,
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output reg [3:0] dmem_wr_o /*verilator public*/,
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output reg [3:0] dmem_sel_o /*verilator public*/,
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output reg dmem_rd_o /*verilator public*/,
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output reg dmem_we_o /*verilator public*/,
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input dmem_accept_i /*verilator public*/,
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output reg dmem_stb_o /*verilator public*/,
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output reg dmem_cyc_o /*verilator public*/,
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input dmem_stall_i /*verilator public*/,
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input dmem_ack_i /*verilator public*/
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input dmem_ack_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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| Line 747... |
Line 747... |
end
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end
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Comparisons
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// Comparisons
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [31:0] compare_a_r;
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reg [31:0] compare_b_r;
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always @ *
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always @ *
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begin
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begin
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compare_result_r = 1'b0;
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compare_a_r = reg_ra_r;
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compare_b_r = reg_rb_r;
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case (1'b1)
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case (1'b1)
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inst_sfeq_w: // l.sfeq
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inst_sfeqi_w, // l.sfeqi
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begin
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inst_sfgesi_w, // l.sfgesi
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if (reg_ra_r == reg_rb_r)
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inst_sfgeui_w, // l.sfgeui
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compare_result_r = 1'b1;
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inst_sfgtsi_w, // l.sfgtsi
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else
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inst_sfgtui_w, // l.sfgtui
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compare_result_r = 1'b0;
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inst_sflesi_w, // l.sflesi
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inst_sfleui_w, // l.sfleui
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inst_sfltsi_w, // l.sfltsi
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inst_sfltui_w, // l.sfltui
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inst_sfnei_w: // l.sfnei
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compare_b_r = int32_r;
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default:
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;
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endcase
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end
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end
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inst_sfeqi_w: // l.sfeqi
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reg compare_equal_r;
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reg compare_gts_r;
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reg compare_gt_r;
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reg compare_lts_r;
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reg compare_lt_r;
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always @ *
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begin
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begin
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if (reg_ra_r == int32_r)
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if (compare_a_r == compare_b_r)
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compare_result_r = 1'b1;
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compare_equal_r = 1'b1;
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else
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else
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compare_result_r = 1'b0;
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compare_equal_r = 1'b0;
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end
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inst_sfges_w: // l.sfges
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compare_lts_r = less_than_signed(compare_a_r, compare_b_r);
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begin
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if (greater_than_equal_signed(reg_ra_r, reg_rb_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfgesi_w: // l.sfgesi
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if (compare_a_r < compare_b_r)
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begin
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compare_lt_r = 1'b1;
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if (greater_than_equal_signed(reg_ra_r, int32_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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else
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compare_result_r = 1'b0;
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compare_lt_r = 1'b0;
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end
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inst_sfgeu_w: // l.sfgeu
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// Greater than (signed)
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begin
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compare_gts_r = ~(compare_lts_r | compare_equal_r);
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if (reg_ra_r >= reg_rb_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfgeui_w: // l.sfgeui
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if (compare_a_r > compare_b_r)
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begin
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compare_gt_r = 1'b1;
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if (reg_ra_r >= int32_r)
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compare_result_r = 1'b1;
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else
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else
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compare_result_r = 1'b0;
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compare_gt_r = 1'b0;
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end
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end
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inst_sfgts_w: // l.sfgts
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always @ *
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begin
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begin
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if (greater_than_signed(reg_ra_r, reg_rb_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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compare_result_r = 1'b0;
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end
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inst_sfgtsi_w: // l.sfgtsi
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case (1'b1)
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begin
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inst_sfeq_w, // l.sfeq
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if (greater_than_signed(reg_ra_r, int32_r) == 1'b1)
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inst_sfeqi_w: // l.sfeqi
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compare_result_r = 1'b1;
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compare_result_r = compare_equal_r;
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else
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compare_result_r = 1'b0;
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end
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inst_sfgtu_w: // l.sfgtu
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inst_sfges_w, // l.sfges
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begin
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inst_sfgesi_w: // l.sfgesi
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if (reg_ra_r > reg_rb_r)
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compare_result_r = compare_gts_r | compare_equal_r;
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfgtui_w: // l.sfgtui
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inst_sfgeu_w, // l.sfgeu
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begin
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inst_sfgeui_w: // l.sfgeui
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if (reg_ra_r > int32_r)
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compare_result_r = compare_gt_r | compare_equal_r;
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfles_w: // l.sfles
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inst_sfgts_w, // l.sfgts
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begin
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inst_sfgtsi_w: // l.sfgtsi
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if (less_than_equal_signed(reg_ra_r, reg_rb_r) == 1'b1)
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compare_result_r = compare_gts_r;
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfgtu_w, // l.sfgtu
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inst_sfgtui_w: // l.sfgtui
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compare_result_r = compare_gt_r;
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inst_sfles_w, // l.sfles
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inst_sflesi_w: // l.sflesi
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inst_sflesi_w: // l.sflesi
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begin
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compare_result_r = compare_lts_r | compare_equal_r;
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if (less_than_equal_signed(reg_ra_r, int32_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfleu_w: // l.sfleu
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inst_sfleu_w, // l.sfleu
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begin
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if (reg_ra_r <= reg_rb_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfleui_w: // l.sfleui
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inst_sfleui_w: // l.sfleui
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begin
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compare_result_r = compare_lt_r | compare_equal_r;
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if (reg_ra_r <= int32_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sflts_w: // l.sflts
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inst_sflts_w, // l.sflts
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begin
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if (less_than_signed(reg_ra_r, reg_rb_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfltsi_w: // l.sfltsi
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inst_sfltsi_w: // l.sfltsi
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begin
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compare_result_r = compare_lts_r;
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if (less_than_signed(reg_ra_r, int32_r) == 1'b1)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfltu_w: // l.sfltu
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inst_sfltu_w, // l.sfltu
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begin
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if (reg_ra_r < reg_rb_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfltui_w: // l.sfltui
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inst_sfltui_w: // l.sfltui
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begin
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compare_result_r = compare_lt_r;
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if (reg_ra_r < int32_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfne_w: // l.sfne
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inst_sfne_w, // l.sfne
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begin
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if (reg_ra_r != reg_rb_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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inst_sfnei_w: // l.sfnei
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inst_sfnei_w: // l.sfnei
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begin
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compare_result_r = ~compare_equal_r;
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if (reg_ra_r != int32_r)
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compare_result_r = 1'b1;
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else
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compare_result_r = 1'b0;
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end
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default:
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default:
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;
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;
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endcase
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endcase
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end
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end
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| Line 1328... |
Line 1264... |
if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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// Data memory
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// Data memory
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dmem_addr_o <= 32'h00000000;
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dmem_addr_o <= 32'h00000000;
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dmem_data_out_o <= 32'h00000000;
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dmem_data_out_o <= 32'h00000000;
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dmem_rd_o <= 1'b0;
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dmem_we_o <= 1'b0;
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dmem_wr_o <= 4'b0000;
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dmem_sel_o <= 4'b0000;
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dmem_stb_o <= 1'b0;
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dmem_cyc_o <= 1'b0;
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|
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r_mem_load <= 1'b0;
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r_mem_load <= 1'b0;
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r_mem_store <= 1'b0;
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r_mem_store <= 1'b0;
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r_mem_access <= 1'b0;
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r_mem_access <= 1'b0;
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| Line 1345... |
Line 1283... |
end
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end
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else
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else
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begin
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begin
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|
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// If memory access accepted by slave
|
// If memory access accepted by slave
|
if (dmem_accept_i)
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if (~dmem_stall_i)
|
begin
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dmem_stb_o <= 1'b0;
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dmem_rd_o <= 1'b0;
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dmem_wr_o <= 4'b0000;
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end
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|
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if (dmem_ack_i)
|
|
dmem_cyc_o <= 1'b0;
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r_mem_access <= 1'b0;
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r_mem_access <= 1'b0;
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d_mem_load <= r_mem_access & r_mem_load;
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d_mem_load <= r_mem_access & r_mem_load;
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|
|
// Pending accesses
|
// Pending accesses
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r_mem_load <= load_pending;
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r_mem_load <= load_pending;
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| Line 1389... |
Line 1326... |
// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
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// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
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load_inst_r:
|
load_inst_r:
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
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dmem_data_out_o <= 32'h00000000;
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dmem_data_out_o <= 32'h00000000;
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dmem_rd_o <= 1'b1;
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dmem_sel_o <= 4'b1111;
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dmem_we_o <= 1'b0;
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dmem_stb_o <= 1'b1;
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dmem_cyc_o <= 1'b1;
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|
|
// Mark load as pending
|
// Mark load as pending
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r_mem_load <= 1'b1;
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r_mem_load <= 1'b1;
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r_mem_access <= 1'b1;
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r_mem_access <= 1'b1;
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|
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| Line 1413... |
Line 1353... |
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
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case (mem_addr_r[1:0])
|
case (mem_addr_r[1:0])
|
2'b00 :
|
2'b00 :
|
begin
|
begin
|
dmem_data_out_o <= {reg_rb_r[7:0],24'h000000};
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dmem_data_out_o <= {reg_rb_r[7:0],24'h000000};
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dmem_wr_o <= 4'b1000;
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dmem_sel_o <= 4'b1000;
|
|
dmem_we_o <= 1'b1;
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dmem_stb_o <= 1'b1;
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|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b01 :
|
2'b01 :
|
begin
|
begin
|
dmem_data_out_o <= {{8'h00,reg_rb_r[7:0]},16'h0000};
|
dmem_data_out_o <= {{8'h00,reg_rb_r[7:0]},16'h0000};
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dmem_wr_o <= 4'b0100;
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dmem_sel_o <= 4'b0100;
|
|
dmem_we_o <= 1'b1;
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|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b10 :
|
2'b10 :
|
begin
|
begin
|
dmem_data_out_o <= {{16'h0000,reg_rb_r[7:0]},8'h00};
|
dmem_data_out_o <= {{16'h0000,reg_rb_r[7:0]},8'h00};
|
dmem_wr_o <= 4'b0010;
|
dmem_sel_o <= 4'b0010;
|
|
dmem_we_o <= 1'b1;
|
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dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b11 :
|
2'b11 :
|
begin
|
begin
|
dmem_data_out_o <= {24'h000000,reg_rb_r[7:0]};
|
dmem_data_out_o <= {24'h000000,reg_rb_r[7:0]};
|
dmem_wr_o <= 4'b0001;
|
dmem_sel_o <= 4'b0001;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
default :
|
default :
|
begin
|
;
|
dmem_data_out_o <= 32'h00000000;
|
|
dmem_wr_o <= 4'b0000;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_sh_w: // l.sh
|
inst_sh_w: // l.sh
|
begin
|
begin
|
| Line 1450... |
Line 1399... |
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
case (mem_addr_r[1:0])
|
case (mem_addr_r[1:0])
|
2'b00 :
|
2'b00 :
|
begin
|
begin
|
dmem_data_out_o <= {reg_rb_r[15:0],16'h0000};
|
dmem_data_out_o <= {reg_rb_r[15:0],16'h0000};
|
dmem_wr_o <= 4'b1100;
|
dmem_sel_o <= 4'b1100;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
2'b10 :
|
2'b10 :
|
begin
|
begin
|
dmem_data_out_o <= {16'h0000,reg_rb_r[15:0]};
|
dmem_data_out_o <= {16'h0000,reg_rb_r[15:0]};
|
dmem_wr_o <= 4'b0011;
|
dmem_sel_o <= 4'b0011;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
end
|
end
|
default :
|
default :
|
begin
|
;
|
dmem_data_out_o <= 32'h00000000;
|
|
dmem_wr_o <= 4'b0000;
|
|
end
|
|
endcase
|
endcase
|
end
|
end
|
|
|
inst_sw_w: // l.sw
|
inst_sw_w: // l.sw
|
begin
|
begin
|
dmem_addr_o <= mem_addr_r;
|
dmem_addr_o <= mem_addr_r;
|
dmem_data_out_o <= reg_rb_r;
|
dmem_data_out_o <= reg_rb_r;
|
dmem_wr_o <= 4'b1111;
|
dmem_sel_o <= 4'b1111;
|
|
dmem_we_o <= 1'b1;
|
|
dmem_stb_o <= 1'b1;
|
|
dmem_cyc_o <= 1'b1;
|
r_mem_access <= 1'b1;
|
r_mem_access <= 1'b1;
|
r_mem_store <= 1'b1;
|
r_mem_store <= 1'b1;
|
|
|
`ifdef CONF_CORE_DEBUG
|
`ifdef CONF_CORE_DEBUG
|
$display(" Store R%d to 0x%08x = 0x%08x", reg_rb_i, {mem_addr_r[31:2],2'b00}, reg_rb_r);
|
$display(" Store R%d to 0x%08x = 0x%08x", reg_rb_i, {mem_addr_r[31:2],2'b00}, reg_rb_r);
|
| Line 1617... |
Line 1572... |
get_putc = r_putc;
|
get_putc = r_putc;
|
`else
|
`else
|
get_putc = 8'b0;
|
get_putc = 8'b0;
|
`endif
|
`endif
|
endfunction
|
endfunction
|
|
function [0:0] get_reg_valid;
|
|
// verilator public
|
|
get_reg_valid = ~(resolve_failed | load_stall);
|
|
endfunction
|
|
function [4:0] get_reg_ra;
|
|
// verilator public
|
|
get_reg_ra = reg_ra_i;
|
|
endfunction
|
|
function [31:0] get_reg_ra_value;
|
|
// verilator public
|
|
get_reg_ra_value = ra_value_resolved;
|
|
endfunction
|
|
function [4:0] get_reg_rb;
|
|
// verilator public
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get_reg_rb = reg_rb_i;
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endfunction
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function [31:0] get_reg_rb_value;
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// verilator public
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get_reg_rb_value = rb_value_resolved;
|
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endfunction
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`endif
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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