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[/] [altor32/] [trunk/] [rtl/] [cpu/] [altor32_exec.v] - Diff between revs 40 and 44

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Rev 40 Rev 44
Line 48... Line 48... 
    input               rst_i /*verilator public*/,
 
    input               rst_i /*verilator public*/,
 
 
 
 
 
    // Maskable interrupt    
    // Maskable interrupt    
    input               intr_i /*verilator public*/,
 
    input               intr_i /*verilator public*/,
 
 
 
 
 
    // Unmaskable interrupt
 
    // Break interrupt
 
    input               nmi_i /*verilator public*/,
 
    input               break_i /*verilator public*/,
 
 
 
 
 
    // Fault
 
    // Fault
 
    output reg          fault_o /*verilator public*/,
 
    output reg          fault_o /*verilator public*/,
 
 
 
 
 
    // Breakpoint / Trap
 
    // Breakpoint / Trap
Line 192... Line 192... 
wire        load_insert_w;
 
wire        load_insert_w;
 
wire        load_stall_w;
 
wire        load_stall_w;
 
 
 
 
 
reg         d_mem_load_q;
 
reg         d_mem_load_q;
 
 
 
 
 
// Delayed NMI
 
reg         break_q;
 
reg         nmi_q;
 
 
 
 
 
 
 
// Exception/Interrupt was last instruction
 
// Exception/Interrupt was last instruction
 
reg         exc_last_q;
 
reg         exc_last_q;
 
 
 
 
 
// SIM PUTC
 
// SIM PUTC
Line 499... Line 498... 
        next_sr_r[`SR_CY] = alu_carry_out_w;
 
        next_sr_r[`SR_CY] = alu_carry_out_w;
 
 
 
 
 
    // If valid instruction, check if SR needs updating
 
    // If valid instruction, check if SR needs updating
 
    if (execute_inst_r & ~stall_inst_r)
 
    if (execute_inst_r & ~stall_inst_r)
 
    begin
 
    begin
 
 
 
 
 
 
 
      // Clear step control (if not executing higher priority syscall/break)
 
 
 
      if (!inst_sys_w && !inst_trap_w)
 
 
 
          next_sr_r[`SR_STEP] = 1'b0;
 
 
 
 
 
      case (1'b1)
 
      case (1'b1)
 
      inst_mtspr_w:
 
      inst_mtspr_w:
 
      begin
 
      begin
 
          case (mxspr_uint16_r)
 
          case (mxspr_uint16_r)
 
          // SR - Supervision register
 
          // SR - Supervision register
Line 1184... Line 1188... 
       sr_q                 <= 32'h00000000;
 
       sr_q                 <= 32'h00000000;
 
       esr_q                <= 32'h00000000;
 
       esr_q                <= 32'h00000000;
 
 
 
 
 
       fault_o              <= 1'b0;
 
       fault_o              <= 1'b0;
 
 
 
 
 
       nmi_q                <= 1'b0;
 
       break_q              <= 1'b0;
 
 
 
       break_o              <= 1'b0;
 
   end
 
   end
 
   else
 
   else
 
   begin
 
   begin
 
      // Record NMI in-case it can't be processed this cycle
 
      // Flop break request, clear when break interrupt executed
 
      if (nmi_i)
 
      if (break_i)
 
          nmi_q             <= 1'b1;
 
          break_q           <= 1'b1;
 
 
 
 
 
       // Reset branch request
 
       // Reset branch request
 
       pc_fetch_q           <= 1'b0;
 
       pc_fetch_q           <= 1'b0;
 
       exc_last_q           <= 1'b0;
 
       exc_last_q           <= 1'b0;
 
 
 
 
 
 
 
       break_o              <= 1'b0;
 
 
 
 
 
       // Update SR
 
       // Update SR
 
       sr_q                 <= next_sr_r;
 
       sr_q                 <= next_sr_r;
 
 
 
 
 
       // Update EPC / ESR which may have been updated by an 
       // Update EPC / ESR which may have been updated by an 
       // MTSPR write / flag update in instruction after interrupt
 
       // MTSPR write / flag update in instruction after interrupt
Line 1234... Line 1241... 
           begin
 
           begin
 
                // Save PC of next instruction
 
                // Save PC of next instruction
 
                epc_q       <= next_pc_r;
 
                epc_q       <= next_pc_r;
 
                esr_q       <= next_sr_r;
 
                esr_q       <= next_sr_r;
 
 
 
 
 
                // Disable further interrupts
 
                // Disable further interrupts / break events
 
                sr_q        <= 32'b0;
 
                sr_q        <= 32'b0;
 
 
 
 
 
                // Set PC to exception vector
 
                // Set PC to exception vector
 
                pc_branch_q <= branch_target_r;
 
                pc_branch_q <= branch_target_r;
 
                pc_fetch_q  <= 1'b1;
 
                pc_fetch_q  <= 1'b1;
 
                exc_last_q  <= 1'b1;
 
                exc_last_q  <= 1'b1;
 
 
 
 
 
 
 
                if (inst_trap_w)
 
 
 
                    break_o     <= 1'b1;
 
 
 
 
 
    `ifdef CONF_CORE_DEBUG
 
    `ifdef CONF_CORE_DEBUG
 
               $display(" Exception 0x%08x", branch_target_r);
 
               $display(" Exception 0x%08x", branch_target_r);
 
    `endif
 
    `endif
 
           end
 
           end
 
           // Non-maskable interrupt
 
           // Single step / break request
 
           else if (nmi_i | nmi_q)
 
           else if ((sr_q[`SR_STEP] || break_q) && sr_q[`SR_DBGEN])
 
           begin
 
           begin
 
                nmi_q       <= 1'b0;
 
 
 
 
 
 
 
                // Save PC of next instruction
 
                // Save PC of next instruction
 
                if (branch_r)
 
                if (branch_r)
 
                    epc_q <= branch_target_r;
 
                    epc_q <= branch_target_r;
 
                // Next expected PC (current PC + 4)
 
                // Next expected PC (current PC + 4)
 
                else
 
                else
 
                    epc_q <= next_pc_r;
 
                    epc_q <= next_pc_r;
 
 
 
 
 
 
 
                // Save SR
 
                esr_q       <= next_sr_r;
 
                esr_q       <= next_sr_r;
 
 
 
 
 
                // Disable further interrupts
 
                // Disable further interrupts / break events
 
                sr_q        <= 32'b0;
 
                sr_q        <= 32'b0;
 
 
 
                break_q     <= 1'b0;
 
 
 
                break_o     <= 1'b1;
 
 
 
 
 
                // Set PC to exception vector
 
                // Set PC to trap vector
 
                pc_branch_q <= ISR_VECTOR + `VECTOR_NMI;
 
                pc_branch_q <= ISR_VECTOR + `VECTOR_TRAP;
 
                pc_fetch_q  <= 1'b1;
 
                pc_fetch_q  <= 1'b1;
 
                exc_last_q  <= 1'b1;
 
                exc_last_q  <= 1'b1;
 
 
 
 
 
    `ifdef CONF_CORE_DEBUG
 
    `ifdef CONF_CORE_DEBUG
 
               $display(" NMI 0x%08x", ISR_VECTOR + `VECTOR_NMI);
 
               $display(" Break Event 0x%08x", ISR_VECTOR + `VECTOR_TRAP);
 
    `endif
 
    `endif
 
           end
 
           end
 
           // External interrupt
 
           // External interrupt
 
           else if (intr_i && next_sr_r[`SR_IEE])
 
           else if (intr_i && next_sr_r[`SR_IEE])
 
           begin
 
           begin
Line 1284... Line 1295... 
                else
 
                else
 
                    epc_q <= next_pc_r;
 
                    epc_q <= next_pc_r;
 
 
 
 
 
                esr_q       <= next_sr_r;
 
                esr_q       <= next_sr_r;
 
 
 
 
 
                // Disable further interrupts
 
                // Disable further interrupts / break events
 
                sr_q        <= 32'b0;
 
                sr_q        <= 32'b0;
 
 
 
 
 
                // Set PC to external interrupt vector
 
                // Set PC to external interrupt vector
 
                pc_branch_q <= ISR_VECTOR + `VECTOR_EXTINT;
 
                pc_branch_q <= ISR_VECTOR + `VECTOR_EXTINT;
 
                pc_fetch_q  <= 1'b1;
 
                pc_fetch_q  <= 1'b1;
Line 1506... Line 1517... 
//-----------------------------------------------------------------
 
//-----------------------------------------------------------------
 
always @ (posedge clk_i or posedge rst_i)
 
always @ (posedge clk_i or posedge rst_i)
 
begin
 
begin
 
   if (rst_i == 1'b1)
 
   if (rst_i == 1'b1)
 
   begin
 
   begin
 
       break_o              <= 1'b0;
 
 
 
       icache_flush_o       <= 1'b0;
 
       icache_flush_o       <= 1'b0;
 
       dcache_flush_o       <= 1'b0;
 
       dcache_flush_o       <= 1'b0;
 
   end
 
   end
 
   else
 
   else
 
   begin
 
   begin
 
       break_o              <= 1'b0;
 
 
 
       icache_flush_o       <= 1'b0;
 
       icache_flush_o       <= 1'b0;
 
       dcache_flush_o       <= 1'b0;
 
       dcache_flush_o       <= 1'b0;
 
 
 
 
 
       //---------------------------------------------------------------
 
       //---------------------------------------------------------------
 
       // Valid instruction
 
       // Valid instruction
Line 1534... Line 1543... 
                       icache_flush_o <= reg_rb_r[`SR_ICACHE_FLUSH];
 
                       icache_flush_o <= reg_rb_r[`SR_ICACHE_FLUSH];
 
                       dcache_flush_o <= reg_rb_r[`SR_DCACHE_FLUSH];
 
                       dcache_flush_o <= reg_rb_r[`SR_DCACHE_FLUSH];
 
                   end
 
                   end
 
               endcase
 
               endcase
 
          end
 
          end
 
 
 
 
 
          inst_trap_w: // l.trap
 
 
 
              break_o <= 1'b1;
 
 
 
          default:
 
          default:
 
              ;
 
              ;
 
         endcase
 
         endcase
 
       end
 
       end
 
   end
 
   end

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