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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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Line 79... |
parameter PIPELINED_FETCH = "DISABLED";
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parameter PIPELINED_FETCH = "DISABLED";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg r_rd;
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reg rd_q;
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reg [31:0] r_pc;
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reg [31:0] pc_q;
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reg [31:0] d_pc;
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reg [31:0] pc_last_q;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Next PC state machine
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// Next PC state machine
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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wire [31:0] next_pc = r_pc + 32'd4;
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wire [31:0] next_pc_w = pc_q + 32'd4;
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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r_pc <= BOOT_VECTOR + `VECTOR_RESET;
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pc_q <= BOOT_VECTOR + `VECTOR_RESET;
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d_pc <= BOOT_VECTOR + `VECTOR_RESET;
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pc_last_q <= BOOT_VECTOR + `VECTOR_RESET;
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r_rd <= 1'b1;
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rd_q <= 1'b1;
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end
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end
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else if (~stall_i)
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else if (~stall_i)
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begin
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begin
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r_rd <= 1'b0;
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d_pc <= pc_o;
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// Branch - Next PC = branch target + 4
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// Branch - Next PC = branch target + 4
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if (branch_i)
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if (branch_i)
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begin
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begin
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r_pc <= branch_pc_i + 4;
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rd_q <= 1'b0;
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pc_last_q <= pc_o;
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pc_q <= branch_pc_i + 4;
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end
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end
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// Normal sequential execution (and instruction is ready)
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// Normal sequential execution (and instruction is ready)
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else if (data_valid_i)
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else if (data_valid_i)
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begin
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begin
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// New cache line?
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// New cache line?
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if (next_pc[CACHE_LINE_SIZE_WIDTH-1:0] == {CACHE_LINE_SIZE_WIDTH{1'b0}})
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if (next_pc_w[CACHE_LINE_SIZE_WIDTH-1:0] == {CACHE_LINE_SIZE_WIDTH{1'b0}})
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begin
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rd_q <= 1'b1;
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// Start fetch of next line
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else
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r_rd <= 1'b1;
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rd_q <= 1'b0;
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end
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r_pc <= next_pc;
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pc_last_q <= pc_o;
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pc_q <= next_pc_w;
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end
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else
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begin
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rd_q <= 1'b0;
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pc_last_q <= pc_o;
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end
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end
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end
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end
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end
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end
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Assignments
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//-------------------------------------------------------------------
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// Instruction Fetch
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// Instruction Fetch
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//-------------------------------------------------------------------
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always @ *
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always @ *
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begin
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begin
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// Stall, revert to last requested PC
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// Stall, revert to last requested PC
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if (stall_i)
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if (stall_i)
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pc_o = d_pc;
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pc_o = pc_last_q;
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else if (branch_i)
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else if (branch_i)
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pc_o = branch_pc_i;
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pc_o = branch_pc_i;
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else if (~data_valid_i)
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else if (~data_valid_i)
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pc_o = d_pc;
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pc_o = pc_last_q;
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else
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else
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pc_o = r_pc;
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pc_o = pc_q;
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end
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end
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assign fetch_o = branch_i ? 1'b1 : r_rd;
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assign fetch_o = branch_i ? 1'b1 : rd_q;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Opcode output (retiming)
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// Opcode output (retiming)
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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generate
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generate
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if (PIPELINED_FETCH == "ENABLED")
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if (PIPELINED_FETCH == "ENABLED")
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begin: FETCH_FLOPS
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begin: FETCH_FLOPS
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reg [31:0] r_opcode;
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reg [31:0] opcode_q;
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reg [31:0] r_opcode_pc;
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reg [31:0] opcode_pc_q;
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reg r_opcode_valid;
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reg opcode_valid_q;
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reg r_branch;
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reg branch_q;
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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r_opcode <= 32'b0;
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opcode_q <= 32'b0;
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r_opcode_pc <= 32'b0;
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opcode_pc_q <= 32'b0;
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r_opcode_valid <= 1'b0;
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opcode_valid_q <= 1'b0;
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r_branch <= 1'b0;
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branch_q <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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r_branch <= branch_i;
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branch_q <= branch_i;
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if (~stall_i)
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if (~stall_i)
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begin
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begin
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r_opcode_pc <= d_pc;
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opcode_pc_q <= pc_last_q;
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r_opcode <= data_i;
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opcode_q <= data_i;
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r_opcode_valid <= (data_valid_i & !branch_i);
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opcode_valid_q <= (data_valid_i & !branch_i);
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end
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end
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end
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end
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end
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end
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// Opcode output
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// Opcode output
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assign opcode_valid_o = r_opcode_valid & ~branch_i & ~r_branch;
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assign opcode_valid_o = opcode_valid_q & ~branch_i & ~branch_q;
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assign opcode_o = r_opcode;
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assign opcode_o = opcode_q;
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assign opcode_pc_o = r_opcode_pc;
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assign opcode_pc_o = opcode_pc_q;
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end
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end
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Opcode output
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// Opcode output
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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else
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else
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begin : NO_FETCH_FLOPS
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begin : NO_FETCH_FLOPS
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// Opcode output
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assign opcode_valid_o = (data_valid_i & !branch_i);
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assign opcode_valid_o = (data_valid_i & !branch_i);
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assign opcode_o = data_i;
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assign opcode_o = data_i;
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assign opcode_pc_o = d_pc;
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assign opcode_pc_o = pc_last_q;
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end
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end
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endgenerate
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endgenerate
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Opcode output
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// Opcode output
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// If simulation, RA = 03 if NOP instruction
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// If simulation, RA = 03 if NOP instruction
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`ifdef SIMULATION
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`ifdef SIMULATION
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wire [7:0] v_fetch_inst = {2'b00, opcode_o[31:26]};
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wire [7:0] fetch_inst_w = {2'b00, opcode_o[31:26]};
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wire v_is_nop = (v_fetch_inst == `INST_OR32_NOP);
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wire nop_inst_w = (fetch_inst_w == `INST_OR32_NOP);
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assign ra_o = v_is_nop ? 5'd3 : opcode_o[20:16];
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assign ra_o = nop_inst_w ? 5'd3 : opcode_o[20:16];
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`else
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`else
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assign ra_o = opcode_o[20:16];
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assign ra_o = opcode_o[20:16];
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`endif
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`endif
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assign rb_o = opcode_o[15:11];
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assign rb_o = opcode_o[15:11];
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