| Line 58... |
Line 58... |
// Status
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// Status
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output miss_o /*verilator public*/,
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output miss_o /*verilator public*/,
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output busy_o /*verilator public*/,
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output busy_o /*verilator public*/,
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// Memory interface (slave)
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// Memory interface (slave)
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output [31:0] mem_addr_o /*verilator public*/,
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output reg [31:0] mem_addr_o /*verilator public*/,
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input [31:0] mem_data_i /*verilator public*/,
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input [31:0] mem_data_i /*verilator public*/,
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output mem_burst_o /*verilator public*/,
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output reg mem_burst_o /*verilator public*/,
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output mem_rd_o /*verilator public*/,
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output reg mem_rd_o /*verilator public*/,
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input mem_accept_i/*verilator public*/,
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input mem_accept_i/*verilator public*/,
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input mem_ack_i/*verilator public*/
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input mem_ack_i/*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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| Line 114... |
Line 114... |
reg [CACHE_LINE_SIZE_WIDTH-3:0] fetch_word;
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reg [CACHE_LINE_SIZE_WIDTH-3:0] fetch_word;
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reg [31:0] last_pc;
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reg [31:0] last_pc;
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reg [31:0] miss_pc;
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reg [31:0] miss_pc;
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wire busy_o;
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wire miss_o;
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reg initial_fetch;
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reg initial_fetch;
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reg flush_req;
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reg flush_req;
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reg [31:0] mem_addr_o;
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reg mem_rd_o;
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reg mem_burst_o;
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reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr;
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reg [CACHE_LINE_ADDR_WIDTH-1:0] flush_addr;
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reg flush_wr;
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reg flush_wr;
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reg read_while_busy;
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reg read_while_busy;
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| Line 142... |
Line 135... |
assign tag_entry = (state != STATE_CHECK) ? miss_pc[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] : pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign tag_entry = (state != STATE_CHECK) ? miss_pc[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH] : pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:CACHE_LINE_SIZE_WIDTH];
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assign cache_address_rd = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
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assign cache_address_rd = pc_i[CACHE_LINE_ADDR_WIDTH + CACHE_LINE_SIZE_WIDTH - 1:2];
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assign miss_o = (!tag_data_out[CACHE_TAG_VALID_BIT] || (last_pc[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_data_out[14:0])) ? 1'b1: 1'b0;
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assign miss_o = (!tag_data_out[CACHE_TAG_VALID_BIT] || (last_pc[CACHE_TAG_ADDR_HIGH:CACHE_TAG_ADDR_LOW] != tag_data_out[14:0])) ? 1'b1: 1'b0;
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wire valid_o = !miss_o && !busy_o;
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assign valid_o = !miss_o && !busy_o;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Control logic
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// Control logic
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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reg [CACHE_LINE_SIZE_WIDTH-3:0] v_line_word;
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reg [CACHE_LINE_SIZE_WIDTH-3:0] v_line_word;
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