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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// AltOR32
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// Alternative Lightweight OpenRisc
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// Alternative Lightweight OpenRisc
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// V2.0
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// V2.1
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// Ultra-Embedded.com
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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// Copyright 2011 - 2014
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//
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//
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// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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input rd_i /*verilator public*/,
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input rd_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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input [31:0] pc_i /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output [31:0] instruction_o /*verilator public*/,
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output valid_o /*verilator public*/,
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output valid_o /*verilator public*/,
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// Invalidate (not used)
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input invalidate_i /*verilator public*/,
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// Memory interface
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// Memory interface
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output reg [31:0] wbm_addr_o /*verilator public*/,
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output reg [31:0] wbm_addr_o /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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input [31:0] wbm_dat_i /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output [2:0] wbm_cti_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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output reg wbm_cyc_o /*verilator public*/,
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assign wbm_cti_o = 3'b111;
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assign wbm_cti_o = 3'b111;
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endmodule
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endmodule
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