| Line 62... |
Line 62... |
input [31:0] mem_result_i /*verilator public*/,
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input [31:0] mem_result_i /*verilator public*/,
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input [1:0] mem_offset_i /*verilator public*/,
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input [1:0] mem_offset_i /*verilator public*/,
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input mem_ready_i /*verilator public*/,
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input mem_ready_i /*verilator public*/,
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|
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// Multiplier result
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// Multiplier result
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input mult_i /*verilator public*/,
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input [63:0] mult_result_i /*verilator public*/,
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input [31:0] mult_result_i /*verilator public*/,
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// Outputs
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// Outputs
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output write_enable_o /*verilator public*/,
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output reg write_enable_o /*verilator public*/,
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output [4:0] write_addr_o /*verilator public*/,
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output reg [4:0] write_addr_o /*verilator public*/,
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output [31:0] write_data_o /*verilator public*/
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output reg [31:0] write_data_o /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers / Wires
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Register address
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// Register address
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reg [4:0] rd_q;
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reg [4:0] rd_q;
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| Line 86... |
Line 85... |
reg [7:0] opcode_q;
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reg [7:0] opcode_q;
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// Register writeback enable
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// Register writeback enable
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reg write_rd_q;
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reg write_rd_q;
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|
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reg [1:0] mem_offset_q;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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// Writeback
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// Pipeline Registers
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i == 1'b1)
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if (rst_i == 1'b1)
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begin
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begin
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write_rd_q <= 1'b1;
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write_rd_q <= 1'b1;
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result_q <= 32'h00000000;
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result_q <= 32'h00000000;
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rd_q <= 5'b00000;
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rd_q <= 5'b00000;
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opcode_q <= 8'b0;
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opcode_q <= 8'b0;
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mem_offset_q <= 2'b0;
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end
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end
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else
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else
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begin
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begin
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rd_q <= rd_i;
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rd_q <= rd_i;
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result_q <= alu_result_i;
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result_q <= alu_result_i;
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|
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opcode_q <= {2'b00,opcode_i[31:26]};
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opcode_q <= {2'b00,opcode_i[31:26]};
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mem_offset_q<= mem_offset_i;
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|
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// Register writeback required?
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// Register writeback required?
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if (rd_i != 5'b00000)
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if (rd_i != 5'b00000)
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write_rd_q <= 1'b1;
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write_rd_q <= 1'b1;
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else
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else
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| Line 127... |
Line 130... |
// Opcode
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// Opcode
|
.opcode_i(opcode_q),
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.opcode_i(opcode_q),
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|
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// Memory load result
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// Memory load result
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.mem_result_i(mem_result_i),
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.mem_result_i(mem_result_i),
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.mem_offset_i(mem_offset_i),
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.mem_offset_i(mem_offset_q),
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|
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// Result
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// Result
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.load_result_o(load_result_w),
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.load_result_o(load_result_w),
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.load_insn_o(load_inst_w)
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.load_insn_o(load_inst_w)
|
);
|
);
|
|
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
// Assignments
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// Writeback
|
//-------------------------------------------------------------------
|
//-------------------------------------------------------------------
|
assign write_enable_o = load_inst_w ? (write_rd_q & mem_ready_i) : write_rd_q;
|
always @ *
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assign write_data_o = load_inst_w ? load_result_w : (mult_i ? mult_result_i : result_q);
|
begin
|
assign write_addr_o = rd_q;
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write_addr_o = rd_q;
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|
|
|
// Load result
|
|
if (load_inst_w)
|
|
begin
|
|
write_enable_o = write_rd_q & mem_ready_i;
|
|
write_data_o = load_result_w;
|
|
end
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// Normal ALU instruction
|
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else
|
|
begin
|
|
write_enable_o = write_rd_q;
|
|
write_data_o = result_q;
|
|
end
|
|
end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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