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Line 8... |
// Email: admin@ultra-embedded.com
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// Email: admin@ultra-embedded.com
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//
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//
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// License: LGPL
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// License: LGPL
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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// Copyright (C) 2011 - 2014 Ultra-Embedded.com
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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Line 46... |
module altor32_regfile_alt
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module altor32_regfile_alt
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(
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(
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input clk_i /*verilator public*/,
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input clk_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input rst_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input wr_i /*verilator public*/,
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input [4:0] rs_i /*verilator public*/,
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input [4:0] ra_i /*verilator public*/,
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input [4:0] rt_i /*verilator public*/,
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input [4:0] rb_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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input [4:0] rd_i /*verilator public*/,
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output reg [31:0] reg_rs_o /*verilator public*/,
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output reg [31:0] reg_ra_o /*verilator public*/,
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output reg [31:0] reg_rt_o /*verilator public*/,
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output reg [31:0] reg_rb_o /*verilator public*/,
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input [31:0] reg_rd_i /*verilator public*/
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input [31:0] reg_rd_i /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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Line 62... |
parameter SUPPORT_32REGS = "ENABLED";
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parameter SUPPORT_32REGS = "ENABLED";
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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wire clk_delayed;
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wire clk_delayed_w;
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wire [31:0] data_out1;
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wire [31:0] reg_ra_w;
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wire [31:0] data_out2;
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wire [31:0] reg_rb_w;
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reg write_enable;
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wire write_enable_w;
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reg [4:0] addr_reg;
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reg [4:0] addr_q;
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reg [31:0] data_reg;
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reg [31:0] data_q;
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wire [31:0] q1;
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wire [31:0] ra_w;
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wire [31:0] q2;
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wire [31:0] rb_w;
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//-----------------------------------------------------------------
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// Async Read Process
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//-----------------------------------------------------------------
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always @ (clk_i or rs_i or rt_i or rd_i or reg_rd_i or data_out1 or data_out2 or rst_i or wr_i)
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begin
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// Read Rs
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if (rs_i == 5'b00000)
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reg_rs_o <= 32'h00000000;
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else
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reg_rs_o <= data_out1;
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// Read Rt
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if (rt_i == 5'b00000)
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reg_rt_o <= 32'h00000000;
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else
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reg_rt_o <= data_out2;
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// Write enabled?
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if ((rd_i != 5'b00000) & (wr_i == 1'b1))
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write_enable <= 1'b1;
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else
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write_enable <= 1'b0;
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end
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Sync addr & data
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// Sync addr & data
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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begin
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begin
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if (rst_i)
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if (rst_i)
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begin
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begin
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addr_reg <= 5'b00000;
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addr_q <= 5'b00000;
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data_reg <= 32'h00000000;
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data_q <= 32'h00000000;
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|
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end
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end
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else
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else
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begin
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begin
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addr_reg <= rd_i;
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addr_q <= rd_i;
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data_reg <= reg_rd_i;
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data_q <= reg_rd_i;
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end
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end
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end
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end
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|
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Register File (using lpm_ram_dp)
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// Register File (using lpm_ram_dp)
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Line 113... |
.lpm_type("lpm_ram_dp"),
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.lpm_type("lpm_ram_dp"),
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.lpm_hint("UNUSED")
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.lpm_hint("UNUSED")
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)
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)
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lpm1
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lpm1
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(
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(
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.rdclock(clk_delayed),
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.rdclock(clk_delayed_w),
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.rdclken(1'b1),
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.rdclken(1'b1),
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.rdaddress(rs_i),
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.rdaddress(ra_i),
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.rden(1'b1),
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.rden(1'b1),
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.data(reg_rd_i),
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.data(reg_rd_i),
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.wraddress(rd_i),
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.wraddress(rd_i),
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.wren(write_enable),
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.wren(write_enable_w),
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.wrclock(clk_i),
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.wrclock(clk_i),
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.wrclken(1'b1),
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.wrclken(1'b1),
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.q(q1)
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.q(ra_w)
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);
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);
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lpm_ram_dp
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lpm_ram_dp
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#(
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#(
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Line 140... |
.lpm_type("lpm_ram_dp"),
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.lpm_type("lpm_ram_dp"),
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.lpm_hint("UNUSED")
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.lpm_hint("UNUSED")
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)
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)
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lpm2
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lpm2
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(
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(
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.rdclock(clk_delayed),
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.rdclock(clk_delayed_w),
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.rdclken(1'b1),
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.rdclken(1'b1),
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.rdaddress(rt_i),
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.rdaddress(rb_i),
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.rden(1'b1),
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.rden(1'b1),
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.data(reg_rd_i),
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.data(reg_rd_i),
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.wraddress(rd_i),
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.wraddress(rd_i),
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.wren(write_enable),
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.wren(write_enable_w),
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.wrclock(clk_i),
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.wrclock(clk_i),
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.wrclken(1'b1),
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.wrclken(1'b1),
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.q(q2)
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.q(rb_w)
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Combinatorial Assignments
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// Combinatorial Assignments
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Delayed clock
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// Delayed clock
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assign clk_delayed = !clk_i;
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assign clk_delayed_w = !clk_i;
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// Register read ports
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always @ *
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begin
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if (ra_i == 5'b00000)
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reg_ra_o = 32'h00000000;
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else
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reg_ra_o = reg_ra_w;
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if (rb_i == 5'b00000)
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reg_rb_o = 32'h00000000;
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else
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reg_rb_o = reg_rb_w;
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end
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assign write_enable_w = (rd_i != 5'b00000) & wr_i;
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// Reads are bypassed during write-back
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// Reads are bypassed during write-back
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assign data_out1 = (rs_i != addr_reg) ? q1 : data_reg;
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assign reg_ra_w = (ra_i != addr_q) ? ra_w : data_q;
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assign data_out2 = (rt_i != addr_reg) ? q2 : data_reg;
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assign reg_rb_w = (rb_i != addr_q) ? rb_w : data_q;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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