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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module: ram - dual port block RAM
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// Module: ram - dual port block RAM
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module ram
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module ram
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(
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(
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// Port A
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// Port A
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input clka_i /*verilator public*/,
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input clka_i /*verilator public*/,
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input ena_i /*verilator public*/,
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input rsta_i /*verilator public*/,
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input [3:0] wea_i /*verilator public*/,
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input stba_i /*verilator public*/,
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input wea_i /*verilator public*/,
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input [3:0] sela_i /*verilator public*/,
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input [31:2] addra_i /*verilator public*/,
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input [31:2] addra_i /*verilator public*/,
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input [31:0] dataa_i /*verilator public*/,
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input [31:0] dataa_i /*verilator public*/,
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output [31:0] dataa_o /*verilator public*/,
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output [31:0] dataa_o /*verilator public*/,
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output reg acka_o /*verilator public*/,
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// Port B
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// Port B
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input clkb_i /*verilator public*/,
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input clkb_i /*verilator public*/,
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input enb_i /*verilator public*/,
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input rstb_i /*verilator public*/,
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input [3:0] web_i /*verilator public*/,
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input stbb_i /*verilator public*/,
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input web_i /*verilator public*/,
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input [3:0] selb_i /*verilator public*/,
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input [31:2] addrb_i /*verilator public*/,
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input [31:2] addrb_i /*verilator public*/,
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input [31:0] datab_i /*verilator public*/,
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input [31:0] datab_i /*verilator public*/,
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output [31:0] datab_o /*verilator public*/
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output [31:0] datab_o /*verilator public*/,
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output reg ackb_o /*verilator public*/
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Instantiation
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// Instantiation
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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wire [3:0] wr_a = {4{stba_i}} & {4{wea_i}} & sela_i;
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wire [3:0] wr_b = {4{stbb_i}} & {4{web_i}} & selb_i;
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ram_dp8
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ram_dp8
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#(
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#(
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.WIDTH(8),
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.WIDTH(8),
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.SIZE(SIZE)
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.SIZE(SIZE)
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)
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)
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(
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(
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.aclk_i(clka_i),
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.aclk_i(clka_i),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.adat_o(dataa_o[7:0]),
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.adat_o(dataa_o[7:0]),
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.adat_i(dataa_i[7:0]),
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.adat_i(dataa_i[7:0]),
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.awr_i(wea_i[0]),
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.awr_i(wr_a[0]),
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.bclk_i(clkb_i),
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.bclk_i(clkb_i),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.bdat_o(datab_o[7:0]),
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.bdat_o(datab_o[7:0]),
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.bdat_i(datab_i[7:0]),
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.bdat_i(datab_i[7:0]),
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.bwr_i(web_i[0])
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.bwr_i(wr_b[0])
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);
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);
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ram_dp8
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ram_dp8
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#(
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#(
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.WIDTH(8),
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.WIDTH(8),
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(
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(
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.aclk_i(clka_i),
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.aclk_i(clka_i),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.adat_o(dataa_o[15:8]),
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.adat_o(dataa_o[15:8]),
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.adat_i(dataa_i[15:8]),
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.adat_i(dataa_i[15:8]),
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.awr_i(wea_i[1]),
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.awr_i(wr_a[1]),
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.bclk_i(clkb_i),
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.bclk_i(clkb_i),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.bdat_o(datab_o[15:8]),
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.bdat_o(datab_o[15:8]),
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.bdat_i(datab_i[15:8]),
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.bdat_i(datab_i[15:8]),
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.bwr_i(web_i[1])
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.bwr_i(wr_b[1])
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);
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);
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ram_dp8
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ram_dp8
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#(
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#(
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.WIDTH(8),
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.WIDTH(8),
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(
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(
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.aclk_i(clka_i),
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.aclk_i(clka_i),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.adat_o(dataa_o[23:16]),
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.adat_o(dataa_o[23:16]),
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.adat_i(dataa_i[23:16]),
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.adat_i(dataa_i[23:16]),
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.awr_i(wea_i[2]),
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.awr_i(wr_a[2]),
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.bclk_i(clkb_i),
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.bclk_i(clkb_i),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.bdat_o(datab_o[23:16]),
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.bdat_o(datab_o[23:16]),
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.bdat_i(datab_i[23:16]),
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.bdat_i(datab_i[23:16]),
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.bwr_i(web_i[2])
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.bwr_i(wr_b[2])
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);
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);
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ram_dp8
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ram_dp8
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#(
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#(
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.WIDTH(8),
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.WIDTH(8),
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(
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(
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.aclk_i(clka_i),
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.aclk_i(clka_i),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.aadr_i(addra_i[SIZE+2-1:2]),
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.adat_o(dataa_o[31:24]),
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.adat_o(dataa_o[31:24]),
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.adat_i(dataa_i[31:24]),
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.adat_i(dataa_i[31:24]),
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.awr_i(wea_i[3]),
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.awr_i(wr_a[3]),
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.bclk_i(clkb_i),
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.bclk_i(clkb_i),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.badr_i(addrb_i[SIZE+2-1:2]),
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.bdat_o(datab_o[31:24]),
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.bdat_o(datab_o[31:24]),
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.bdat_i(datab_i[31:24]),
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.bdat_i(datab_i[31:24]),
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.bwr_i(web_i[3])
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.bwr_i(wr_b[3])
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);
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);
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// AckA
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always @(posedge clka_i or posedge rsta_i)
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begin
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if (rsta_i == 1'b1)
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begin
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acka_o <= 1'b0;
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end
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else
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begin
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acka_o <= stba_i;
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end
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end
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// AckB
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always @(posedge clkb_i or posedge rstb_i)
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begin
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if (rstb_i == 1'b1)
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begin
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ackb_o <= 1'b0;
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end
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else
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begin
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ackb_o <= stbb_i;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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