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[/] [altor32/] [trunk/] [rtl/] [sim/] [top.v] - Diff between revs 27 and 32

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Rev 27 Rev 32
Line 62... Line 62...
// Registers / Wires
// Registers / Wires
//-----------------------------------------------------------------
//-----------------------------------------------------------------
wire [31:0]         soc_addr;
wire [31:0]         soc_addr;
wire [31:0]         soc_data_w;
wire [31:0]         soc_data_w;
wire [31:0]         soc_data_r;
wire [31:0]         soc_data_r;
wire [3:0]          soc_wr;
wire                soc_we;
wire                soc_rd;
wire                soc_stb;
 
wire                soc_ack;
wire                soc_irq;
wire                soc_irq;
 
 
wire[31:0]          dmem_address;
wire[31:0]          dmem_address;
wire[31:0]          dmem_data_w;
wire[31:0]          dmem_data_w;
wire[31:0]          dmem_data_r;
wire[31:0]          dmem_data_r;
wire[3:0]           dmem_wr;
wire[3:0]           dmem_sel;
wire                dmem_rd;
wire[2:0]           dmem_cti;
wire                dmem_burst;
wire                dmem_we;
 
wire                dmem_stb;
 
wire                dmem_cyc;
 
wire                dmem_stall;
wire                dmem_ack;
wire                dmem_ack;
reg                 dmem_req_r;
 
 
 
wire[31:0]          imem_addr;
wire[31:0]          imem_addr;
wire[31:0]          imem_data;
wire[31:0]          imem_data;
wire                imem_rd;
wire[3:0]           imem_sel;
wire                imem_burst;
wire                imem_stb;
 
wire                imem_cyc;
 
wire[2:0]           imem_cti;
 
wire                imem_stall;
wire                imem_ack;
wire                imem_ack;
reg                 imem_req_r;
 
 
 
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Instantiation
// Instantiation
//-----------------------------------------------------------------
//-----------------------------------------------------------------
 
 
Line 94... Line 100...
    .block_count(128) // 1MB
    .block_count(128) // 1MB
)
)
u_ram
u_ram
(
(
    .clka_i(clk_i),
    .clka_i(clk_i),
    .ena_i(1'b1),
    .rsta_i(rst_i),
    .wea_i(4'b0),
    .stba_i(imem_stb),
 
    .wea_i(1'b0),
 
    .sela_i(imem_sel),
    .addra_i(imem_addr[31:2]),
    .addra_i(imem_addr[31:2]),
    .dataa_i(32'b0),
    .dataa_i(32'b0),
    .dataa_o(imem_data),
    .dataa_o(imem_data),
 
    .acka_o(imem_ack),
 
 
    .clkb_i(clk_i),
    .clkb_i(clk_i),
    .enb_i(1'b1),
    .rstb_i(rst_i),
    .web_i(dmem_wr),
    .stbb_i(dmem_stb),
 
    .web_i(dmem_we),
 
    .selb_i(dmem_sel),
    .addrb_i(dmem_address[31:2]),
    .addrb_i(dmem_address[31:2]),
    .datab_i(dmem_data_w),
    .datab_i(dmem_data_w),
    .datab_o(dmem_data_r)
    .datab_o(dmem_data_r),
 
    .ackb_o(dmem_ack)
);
);
 
 
 
 
// CPU
// CPU
cpu_if
cpu_if
#(
#(
    .CLK_KHZ(CLK_KHZ),
    .CLK_KHZ(CLK_KHZ),
    .BOOT_VECTOR(32'h10000000),
    .BOOT_VECTOR(32'h10000000),
Line 131... Line 142...
    .nmi_i(1'b0),
    .nmi_i(1'b0),
    .intr_i(soc_irq),
    .intr_i(soc_irq),
 
 
    // Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
    // Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
    .imem0_addr_o(imem_addr),
    .imem0_addr_o(imem_addr),
    .imem0_rd_o(imem_rd),
    .imem0_data_i(imem_data),
    .imem0_burst_o(imem_burst),
    .imem0_sel_o(imem_sel),
    .imem0_data_in_i(imem_data),
    .imem0_cti_o(imem_cti),
    .imem0_accept_i(1'b1),
    .imem0_cyc_o(imem_cyc),
 
    .imem0_stb_o(imem_stb),
 
    .imem0_stall_i(1'b0),
    .imem0_ack_i(imem_ack),
    .imem0_ack_i(imem_ack),
 
 
    // Data Memory 0 (0x10000000 - 0x10FFFFFF)
    // Data Memory 0 (0x10000000 - 0x10FFFFFF)
    .dmem0_addr_o(dmem_address),
    .dmem0_addr_o(dmem_address),
    .dmem0_data_o(dmem_data_w),
    .dmem0_data_o(dmem_data_w),
    .dmem0_data_i(dmem_data_r),
    .dmem0_data_i(dmem_data_r),
    .dmem0_wr_o(dmem_wr),
    .dmem0_sel_o(dmem_sel),
    .dmem0_rd_o(dmem_rd),
    .dmem0_cti_o(dmem_cti),
    .dmem0_accept_i(1'b1),
    .dmem0_cyc_o(dmem_cyc),
    .dmem0_burst_o(dmem_burst),
    .dmem0_we_o(dmem_we),
 
    .dmem0_stb_o(dmem_stb),
 
    .dmem0_stall_i(1'b0),
    .dmem0_ack_i(dmem_ack),
    .dmem0_ack_i(dmem_ack),
 
 
    // Data Memory 1 (0x11000000 - 0x11FFFFFF)
    // Data Memory 1 (0x11000000 - 0x11FFFFFF)
    .dmem1_addr_o(),
    .dmem1_addr_o(/*open*/),
    .dmem1_data_o(),
    .dmem1_data_o(/*open*/),
    .dmem1_data_i(32'b0),
    .dmem1_data_i(32'b0),
    .dmem1_wr_o(),
    .dmem1_sel_o(/*open*/),
    .dmem1_rd_o(),
    .dmem1_we_o(/*open*/),
    .dmem1_accept_i(1'b1),
    .dmem1_stb_o(/*open*/),
    .dmem1_burst_o(/*open*/),
    .dmem1_cyc_o(/*open*/),
 
    .dmem1_cti_o(/*open*/),
 
    .dmem1_stall_i(1'b0),
    .dmem1_ack_i(1'b1),
    .dmem1_ack_i(1'b1),
 
 
    // Data Memory 2 (0x12000000 - 0x12FFFFFF)
    // Data Memory 2 (0x12000000 - 0x12FFFFFF)
    .dmem2_addr_o(soc_addr),
    .dmem2_addr_o(soc_addr),
    .dmem2_data_o(soc_data_w),
    .dmem2_data_o(soc_data_w),
    .dmem2_data_i(soc_data_r),
    .dmem2_data_i(soc_data_r),
    .dmem2_wr_o(soc_wr),
    .dmem2_sel_o(/*open*/),
    .dmem2_rd_o(soc_rd),
    .dmem2_we_o(soc_we),
    .dmem2_accept_i(1'b1),
    .dmem2_stb_o(soc_stb),
    .dmem2_burst_o(/*open*/),
    .dmem2_cyc_o(/*open*/),
    .dmem2_ack_i(1'b1)
    .dmem2_cti_o(/*open*/),
 
    .dmem2_stall_i(1'b0),
 
    .dmem2_ack_i(soc_ack)
);
);
 
 
// CPU SOC
// CPU SOC
soc
soc
#(
#(
Line 188... Line 207...
 
 
    // Memory Port
    // Memory Port
    .io_addr_i(soc_addr),
    .io_addr_i(soc_addr),
    .io_data_i(soc_data_w),
    .io_data_i(soc_data_w),
    .io_data_o(soc_data_r),
    .io_data_o(soc_data_r),
    .io_wr_i(soc_wr),
    .io_we_i(soc_we),
    .io_rd_i(soc_rd)
    .io_stb_i(soc_stb),
 
    .io_ack_o(soc_ack)
);
);
 
 
// Ack
 
always @(posedge clk_i or posedge rst_i)
 
begin
 
    if (rst_i == 1'b1)
 
    begin
 
        imem_req_r  <= 1'b0;
 
    end
 
    else
 
    begin
 
        imem_req_r  <= imem_rd;
 
    end
 
end
 
 
 
assign imem_ack = imem_req_r;
 
 
 
// Ack
 
always @(posedge clk_i or posedge rst_i)
 
begin
 
    if (rst_i == 1'b1)
 
    begin
 
        dmem_req_r  <= 1'b0;
 
    end
 
    else
 
    begin
 
        dmem_req_r  <= dmem_rd | (|dmem_wr);
 
    end
 
end
 
 
 
assign dmem_ack = dmem_req_r;
 
 
 
endmodule
endmodule
 
 
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