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//-----------------------------------------------------------------
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// AltOR32
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// Alternative Lightweight OpenRisc
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// V2.0
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// Ultra-Embedded.com
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// Copyright 2011 - 2013
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//
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// Email: admin@ultra-embedded.com
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//
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// License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module:
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// Module:
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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module cpu_if
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module cpu_if
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(
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(
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// General - Clocking & Reset
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// General - Clocking & Reset
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clk_i,
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input clk_i,
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rst_i,
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input rst_i,
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// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
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// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
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imem0_addr_o,
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output [31:0] imem0_addr_o,
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imem0_rd_o,
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input [31:0] imem0_data_i,
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imem0_burst_o,
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output [3:0] imem0_sel_o,
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imem0_data_in_i,
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output imem0_stb_o,
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imem0_accept_i,
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output imem0_cyc_o,
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imem0_ack_i,
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output [2:0] imem0_cti_o,
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input imem0_ack_i,
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input imem0_stall_i,
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// Data Memory 0 (0x10000000 - 0x10FFFFFF)
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// Data Memory 0 (0x10000000 - 0x10FFFFFF)
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dmem0_addr_o,
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output [31:0] dmem0_addr_o,
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dmem0_data_o,
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output [31:0] dmem0_data_o,
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dmem0_data_i,
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input [31:0] dmem0_data_i,
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dmem0_wr_o,
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output [3:0] dmem0_sel_o,
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dmem0_rd_o,
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output dmem0_we_o,
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dmem0_burst_o,
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output dmem0_stb_o,
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dmem0_accept_i,
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output dmem0_cyc_o,
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dmem0_ack_i,
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output [2:0] dmem0_cti_o,
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input dmem0_ack_i,
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input dmem0_stall_i,
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// Data Memory 1 (0x11000000 - 0x11FFFFFF)
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// Data Memory 1 (0x11000000 - 0x11FFFFFF)
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dmem1_addr_o,
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output [31:0] dmem1_addr_o,
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dmem1_data_o,
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output [31:0] dmem1_data_o,
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dmem1_data_i,
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input [31:0] dmem1_data_i,
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dmem1_wr_o,
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output [3:0] dmem1_sel_o,
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dmem1_rd_o,
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output dmem1_we_o,
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dmem1_burst_o,
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output dmem1_stb_o,
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dmem1_accept_i,
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output dmem1_cyc_o,
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dmem1_ack_i,
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output [2:0] dmem1_cti_o,
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input dmem1_ack_i,
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input dmem1_stall_i,
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// Data Memory 2 (0x12000000 - 0x12FFFFFF)
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// Data Memory 2 (0x12000000 - 0x12FFFFFF)
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dmem2_addr_o,
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output [31:0] dmem2_addr_o,
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dmem2_data_o,
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output [31:0] dmem2_data_o,
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dmem2_data_i,
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input [31:0] dmem2_data_i,
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dmem2_wr_o,
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output [3:0] dmem2_sel_o,
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dmem2_rd_o,
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output dmem2_we_o,
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dmem2_burst_o,
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output dmem2_stb_o,
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dmem2_accept_i,
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output dmem2_cyc_o,
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dmem2_ack_i,
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output [2:0] dmem2_cti_o,
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input dmem2_ack_i,
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fault_o,
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input dmem2_stall_i,
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break_o,
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intr_i,
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output fault_o,
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nmi_i
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output break_o,
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input intr_i,
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input nmi_i
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Params
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// Params
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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parameter [31:0] CLK_KHZ = 12288;
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parameter CLK_KHZ = 12288;
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parameter ENABLE_ICACHE = "ENABLED";
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parameter ENABLE_ICACHE = "ENABLED";
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parameter ENABLE_DCACHE = "DISABLED";
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parameter ENABLE_DCACHE = "ENABLED";
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parameter BOOT_VECTOR = 0;
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parameter BOOT_VECTOR = 0;
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parameter ISR_VECTOR = 0;
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parameter ISR_VECTOR = 0;
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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parameter REGISTER_FILE_TYPE = "SIMULATION";
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// I/O
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//-----------------------------------------------------------------
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input clk_i /*verilator public*/;
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input rst_i /*verilator public*/;
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// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
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output [31:0] imem0_addr_o /*verilator public*/;
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output imem0_rd_o /*verilator public*/;
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output imem0_burst_o /*verilator public*/;
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input [31:0] imem0_data_in_i /*verilator public*/;
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input imem0_accept_i /*verilator public*/;
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input imem0_ack_i /*verilator public*/;
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// Data Memory 0 (0x10000000 - 0x10FFFFFF)
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output [31:0] dmem0_addr_o /*verilator public*/;
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output [31:0] dmem0_data_o /*verilator public*/;
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input [31:0] dmem0_data_i /*verilator public*/;
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output [3:0] dmem0_wr_o /*verilator public*/;
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output dmem0_rd_o /*verilator public*/;
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output dmem0_burst_o /*verilator public*/;
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input dmem0_accept_i /*verilator public*/;
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input dmem0_ack_i /*verilator public*/;
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// Data Memory 1 (0x11000000 - 0x11FFFFFF)
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output [31:0] dmem1_addr_o /*verilator public*/;
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output [31:0] dmem1_data_o /*verilator public*/;
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input [31:0] dmem1_data_i /*verilator public*/;
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output [3:0] dmem1_wr_o /*verilator public*/;
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output dmem1_rd_o /*verilator public*/;
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output dmem1_burst_o /*verilator public*/;
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input dmem1_accept_i /*verilator public*/;
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input dmem1_ack_i /*verilator public*/;
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// Data Memory 2 (0x12000000 - 0x12FFFFFF)
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output [31:0] dmem2_addr_o /*verilator public*/;
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output [31:0] dmem2_data_o /*verilator public*/;
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input [31:0] dmem2_data_i /*verilator public*/;
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output [3:0] dmem2_wr_o /*verilator public*/;
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output dmem2_rd_o /*verilator public*/;
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output dmem2_burst_o /*verilator public*/;
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input dmem2_accept_i /*verilator public*/;
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input dmem2_ack_i /*verilator public*/;
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output fault_o /*verilator public*/;
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output break_o /*verilator public*/;
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input nmi_i /*verilator public*/;
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input intr_i /*verilator public*/;
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//-----------------------------------------------------------------
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// Registers
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// Registers
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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wire [31:0] cpu_address;
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wire [31:0] dmem_addr;
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wire [3:0] cpu_wr;
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wire [31:0] dmem_data_w;
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wire cpu_rd;
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wire [31:0] dmem_data_r;
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wire cpu_burst;
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wire [3:0] dmem_sel;
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wire [31:0] cpu_data_w;
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wire [2:0] dmem_cti;
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wire [31:0] cpu_data_r;
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wire dmem_cyc;
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wire cpu_accept;
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wire dmem_we;
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wire cpu_ack;
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wire dmem_stb;
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wire dmem_stall;
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wire dmem_ack;
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wire [31:0] imem_address;
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wire [31:0] imem_address;
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wire [31:0] imem_data;
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wire [31:0] imem_data;
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wire imem_rd;
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wire [2:0] imem_cti;
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wire imem_burst;
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wire imem_cyc;
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wire imem_stb;
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wire imem_stall;
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wire imem_ack;
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wire imem_ack;
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wire imem_accept;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// CPU core
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// CPU core
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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cpu
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cpu
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.fault_o(fault_o),
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.fault_o(fault_o),
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.break_o(break_o),
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.break_o(break_o),
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// Instruction memory
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// Instruction memory
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.imem_addr_o(imem_address),
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.imem_addr_o(imem_address),
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.imem_rd_o(imem_rd),
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.imem_dat_i(imem_data),
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.imem_burst_o(imem_burst),
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.imem_cti_o(imem_cti),
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.imem_data_in_i(imem_data),
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.imem_cyc_o(imem_cyc),
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.imem_accept_i(imem_accept),
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.imem_stb_o(imem_stb),
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.imem_stall_i(imem_stall),
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.imem_ack_i(imem_ack),
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.imem_ack_i(imem_ack),
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// Data memory
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// Data memory
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.dmem_addr_o(cpu_address),
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.dmem_addr_o(dmem_addr),
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.dmem_data_out_o(cpu_data_w),
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.dmem_dat_o(dmem_data_w),
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.dmem_data_in_i(cpu_data_r),
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.dmem_dat_i(dmem_data_r),
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.dmem_wr_o(cpu_wr),
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.dmem_sel_o(dmem_sel),
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.dmem_rd_o(cpu_rd),
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.dmem_cti_o(dmem_cti),
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.dmem_burst_o(cpu_burst),
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.dmem_cyc_o(dmem_cyc),
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.dmem_accept_i(cpu_accept),
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.dmem_we_o(dmem_we),
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.dmem_ack_i(cpu_ack)
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.dmem_stb_o(dmem_stb),
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.dmem_stall_i(dmem_stall),
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.dmem_ack_i(dmem_ack)
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);
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);
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Instruction Memory MUX
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// Instruction Memory MUX
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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assign imem0_addr_o = imem_address;
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assign imem0_addr_o = imem_address;
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assign imem0_rd_o = imem_rd;
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assign imem0_sel_o = 4'b1111;
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assign imem0_burst_o = imem_burst;
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assign imem0_stb_o = imem_stb;
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assign imem_data = imem0_data_in_i;
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assign imem0_cyc_o = imem_cyc;
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assign imem_accept = imem0_accept_i;
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assign imem0_cti_o = imem_cti;
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assign imem_data = imem0_data_i;
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assign imem_stall = imem0_stall_i;
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assign imem_ack = imem0_ack_i;
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assign imem_ack = imem0_ack_i;
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Data Memory MUX
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// Data Memory MUX
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// Outputs
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// Outputs
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// 0x10000000 - 0x10FFFFFF
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// 0x10000000 - 0x10FFFFFF
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.out0_addr_o(dmem0_addr_o),
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.out0_addr_o(dmem0_addr_o),
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.out0_data_o(dmem0_data_o),
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.out0_data_o(dmem0_data_o),
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.out0_data_i(dmem0_data_i),
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.out0_data_i(dmem0_data_i),
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.out0_wr_o(dmem0_wr_o),
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.out0_sel_o(dmem0_sel_o),
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.out0_rd_o(dmem0_rd_o),
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.out0_we_o(dmem0_we_o),
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.out0_burst_o(dmem0_burst_o),
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.out0_stb_o(dmem0_stb_o),
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.out0_cyc_o(dmem0_cyc_o),
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.out0_cti_o(dmem0_cti_o),
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.out0_ack_i(dmem0_ack_i),
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.out0_ack_i(dmem0_ack_i),
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.out0_accept_i(dmem0_accept_i),
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.out0_stall_i(dmem0_stall_i),
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// 0x11000000 - 0x11FFFFFF
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// 0x11000000 - 0x11FFFFFF
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.out1_addr_o(dmem1_addr_o),
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.out1_addr_o(dmem1_addr_o),
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.out1_data_o(dmem1_data_o),
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.out1_data_o(dmem1_data_o),
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.out1_data_i(dmem1_data_i),
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.out1_data_i(dmem1_data_i),
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.out1_wr_o(dmem1_wr_o),
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.out1_sel_o(dmem1_sel_o),
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.out1_rd_o(dmem1_rd_o),
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.out1_we_o(dmem1_we_o),
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.out1_burst_o(dmem1_burst_o),
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.out1_stb_o(dmem1_stb_o),
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.out1_cyc_o(dmem1_cyc_o),
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.out1_cti_o(dmem1_cti_o),
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.out1_ack_i(dmem1_ack_i),
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.out1_ack_i(dmem1_ack_i),
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.out1_accept_i(dmem1_accept_i),
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.out1_stall_i(dmem1_stall_i),
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// 0x12000000 - 0x12FFFFFF
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// 0x12000000 - 0x12FFFFFF
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.out2_addr_o(dmem2_addr_o),
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.out2_addr_o(dmem2_addr_o),
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.out2_data_o(dmem2_data_o),
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.out2_data_o(dmem2_data_o),
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.out2_data_i(dmem2_data_i),
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.out2_data_i(dmem2_data_i),
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.out2_wr_o(dmem2_wr_o),
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.out2_sel_o(dmem2_sel_o),
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.out2_rd_o(dmem2_rd_o),
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.out2_we_o(dmem2_we_o),
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.out2_burst_o(dmem2_burst_o),
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.out2_stb_o(dmem2_stb_o),
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.out2_cyc_o(dmem2_cyc_o),
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.out2_cti_o(dmem2_cti_o),
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.out2_ack_i(dmem2_ack_i),
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.out2_ack_i(dmem2_ack_i),
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.out2_accept_i(dmem2_accept_i),
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.out2_stall_i(dmem2_stall_i),
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// Input - CPU core bus
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// Input - CPU core bus
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.mem_addr_i(cpu_address),
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.mem_addr_i(dmem_addr),
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.mem_data_i(cpu_data_w),
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.mem_data_i(dmem_data_w),
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.mem_data_o(cpu_data_r),
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.mem_data_o(dmem_data_r),
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.mem_wr_i(cpu_wr),
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.mem_sel_i(dmem_sel),
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.mem_rd_i(cpu_rd),
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.mem_we_i(dmem_we),
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.mem_burst_i(cpu_burst),
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.mem_stb_i(dmem_stb),
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.mem_ack_o(cpu_ack),
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.mem_cyc_i(dmem_cyc),
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.mem_accept_o(cpu_accept)
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.mem_cti_i(dmem_cti),
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.mem_ack_o(dmem_ack),
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.mem_stall_o(dmem_stall)
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);
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);
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endmodule
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endmodule
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