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Subversion Repositories artificial_neural_network

[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [ann.vhd] - Diff between revs 3 and 6

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Rev 3 Rev 6
Line 48... Line 48...
      run_in  : in  std_logic; -- Start and input data validation
      run_in  : in  std_logic; -- Start and input data validation
      m_en    : in  std_logic; -- Weight and bias memory enable (external interface)
      m_en    : in  std_logic; -- Weight and bias memory enable (external interface)
      m_we    : in  std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
      m_we    : in  std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
      inputs  : in  std_logic_vector(NbitIn-1 downto 0); -- Input data
      inputs  : in  std_logic_vector(NbitIn-1 downto 0); -- Input data
      wdata   : in  std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory write data
      wdata   : in  std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory write data
      addr    : in  std_logic_vector((calculate_lra_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
      addr    : in  std_logic_vector((calculate_addr_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
 
 
      -- Output ports
      -- Output ports
      run_out : out std_logic; -- Output data validation
      run_out : out std_logic; -- Output data validation
      rdata   : out std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory read data
      rdata   : out std_logic_vector(NbitW-1 downto 0);  -- Weight and bias memory read data
      outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data
      outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data

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