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https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk
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run_in : in std_logic; -- Start and input data validation
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run_in : in std_logic; -- Start and input data validation
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m_en : in std_logic; -- Weight and bias memory enable (external interface)
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m_en : in std_logic; -- Weight and bias memory enable (external interface)
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m_we : in std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
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m_we : in std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Weight and bias memory write enable (external interface)
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inputs : in std_logic_vector(NbitIn-1 downto 0); -- Input data
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inputs : in std_logic_vector(NbitIn-1 downto 0); -- Input data
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wdata : in std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory write data
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wdata : in std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory write data
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addr : in std_logic_vector((calculate_lra_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
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addr : in std_logic_vector((calculate_addr_l(NumIn, NumN, Nlayer)+log2(Nlayer))-1 downto 0); -- Weight and bias memory address
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-- Output ports
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-- Output ports
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run_out : out std_logic; -- Output data validation
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run_out : out std_logic; -- Output data validation
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rdata : out std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory read data
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rdata : out std_logic_vector(NbitW-1 downto 0); -- Weight and bias memory read data
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outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data
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outputs : out std_logic_vector(NbitOut-1 downto 0) -- Output data
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