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entity layerSP_top is
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entity layerSP_top is
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generic
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generic
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(
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(
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WBinit : boolean := false;
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NumN : natural := 8; ------- Number of neurons of the layer
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LNum : natural := 0; ------- layer number (needed for initialization)
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NumIn : natural := 64; ------- Number of inputs of each neuron
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NumN : natural := 34; ------- Number of neurons of the layer
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NumIn : natural := 27; ------- Number of inputs of each neuron
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitIn : natural := 8; ------- Bit width of the input data
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NbitW : natural := 32; ------- Bit width of weights and biases
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NbitW : natural := 8; ------- Bit width of weights and biases
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NbitOut : natural := 8; ------- Bit width of the output data
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NbitOut : natural := 12; ------- Bit width of the output data
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lra_l : natural := 11; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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lra_l : natural := 10; ------- Layer RAM address length. It should value log2(NumN)+log2(NumIn)
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wra_l : natural := 5; ------- Weight RAM address length. It should value log2(NumIn)
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wra_l : natural := 6; ------- Weight RAM address length. It should value log2(NumIn)
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bra_l : natural := 6; ------- Bias RAM address length. It should value log2(NumN)
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bra_l : natural := 3; ------- Bias RAM address length. It should value log2(NumN)
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LSbit : natural := 6 ------- Less significant bit of the outputs
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LSbit : natural := 4; ------- Less significant bit of the outputs
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WBinit : boolean := false;
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LNum : natural := 0 ------- layer number (needed for initialization)
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);
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);
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port
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port
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(
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(
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-- Input ports
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-- Input ports
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-- Synchronous read including breg:
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-- Synchronous read including breg:
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process (clk)
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process (clk)
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begin
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begin
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if (clk'event and clk = '1') then
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if (clk'event and clk = '1') then
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--report "addr: " & integer'image(wra_l-1);
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--report "addr: " & integer'image(to_integer(uaddr(wra_l-1 downto 0)) );
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if (m_en = '1') then
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if (m_en = '1') then
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if (b_sel = '1') then
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if (b_sel = '1') then
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rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
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rdata <= breg(to_integer(uaddr(bra_l-1 downto 0))); -- Bias registers selected
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else -- Other RAM selected:
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else -- Other RAM selected:
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rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
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rdata <= outm(to_integer(uaddr(lra_l-1 downto wra_l))); -- Multiplexes RAM outputs
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