--------------------------------------------------------------------------------
---- ----
---- Ethernet Switch on Configurable Logic IP Core ----
---- ----
---- This file is part of the ESoCL project ----
---- http://www.opencores.org/cores/esoc/ ----
---- ----
---- Description: see design description ESoCL_dd_71022001.pdf ----
---- ----
---- To Do: see roadmap description ESoCL_dd_71022001.pdf ----
---- and/or release bulleting ESoCL_rb_71022001.pdf ----
---- ----
---- Author(s): L.Maarsen ----
---- Bert Maarsen, lmaarsen@opencores.org ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
--------------------------------------------------------------------------------
-- Object : Entity work.esoc_search_engine
-- Last modified : Mon Apr 14 12:49:54 2014.
--------------------------------------------------------------------------------
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.package_esoc_configuration.all;
entity esoc_search_engine is
port(
clk_control : in std_logic;
clk_search : in std_logic;
ctrl_address : in std_logic_vector(15 downto 0);
ctrl_rd : in std_logic;
ctrl_rddata : out std_logic_vector(31 downto 0);
ctrl_wait : out std_logic;
ctrl_wr : in std_logic;
ctrl_wrdata : in std_logic_vector(31 downto 0);
reset : in std_logic;
search_eof : in std_logic;
search_key : in std_logic_vector(63 downto 0);
search_port_stalled : in std_logic_vector(esoc_port_count-1 downto 0);
search_result : out std_logic_vector(esoc_port_count-1 downto 0);
search_result_av : out std_logic;
search_sof : in std_logic);
end entity esoc_search_engine;
--------------------------------------------------------------------------------
-- Object : Architecture work.esoc_search_engine.esoc_search
-- Last modified : Mon Apr 14 12:49:54 2014.
--------------------------------------------------------------------------------
architecture esoc_search of esoc_search_engine is
signal q_b : STD_LOGIC_VECTOR(79 downto 0);
signal sa_wren : STD_LOGIC := '1';
signal data_b : STD_LOGIC_VECTOR(79 downto 0);
signal address_b : STD_LOGIC_VECTOR(12 downto 0);
signal wren_a : STD_LOGIC := '1';
signal address_a : STD_LOGIC_VECTOR(12 downto 0);
signal data_a : STD_LOGIC_VECTOR(79 downto 0);
signal q_a : STD_LOGIC_VECTOR(79 downto 0);
signal search_sa_drop_cnt : std_logic;
signal search_entry_age_time : std_logic_vector(11 downto 0);
signal wrreq : STD_LOGIC;
signal data : STD_LOGIC_VECTOR(79 downto 0);
signal wrfull : STD_LOGIC;
signal rdreq : std_logic;
signal q : STD_LOGIC_VECTOR(79 downto 0);
signal rdempty : STD_LOGIC;
signal search_sa_overload_cnt : std_logic;
signal rdusedw : STD_LOGIC_VECTOR(6 downto 0);
signal search_entry_age_time_ena : std_logic;
signal clk_en : std_logic;
signal esoc_clk_en_gen_div : integer;
signal Net_0 : STD_LOGIC;
signal rden_b : STD_LOGIC := '1';
component esoc_search_engine_da
port(
clk_search : in std_logic;
reset : in std_logic;
search_eof : in std_logic;
search_key : in std_logic_vector(63 downto 0);
search_port_stalled : in std_logic_vector(esoc_port_count-1 downto 0);
search_result : out std_logic_vector(esoc_port_count-1 downto 0);
search_result_av : out std_logic;
search_sof : in std_logic;
search_table_address : out STD_LOGIC_VECTOR(12 downto 0);
search_table_data : out STD_LOGIC_VECTOR(79 downto 0);
search_table_q : in STD_LOGIC_VECTOR(79 downto 0);
search_table_rden : out STD_LOGIC;
search_table_wren : out STD_LOGIC);
end component esoc_search_engine_da;
component esoc_search_engine_sa
port(
clk_search : in std_logic;
reset : in std_logic;
search_aging_tick : in std_logic;
search_entry_age_time : in std_logic_vector(11 downto 0);
search_entry_age_time_ena : in std_logic;
search_sa_drop_cnt : out std_logic;
search_sa_store_empty : in std_logic;
search_sa_store_q : in std_logic_vector(79 downto 0);
search_sa_store_rd : out std_logic;
search_sa_store_words : in STD_LOGIC_VECTOR(6 downto 0);
search_table_address : out STD_LOGIC_VECTOR(12 downto 0);
search_table_data : out STD_LOGIC_VECTOR(79 downto 0);
search_table_q : in STD_LOGIC_VECTOR(79 downto 0);
search_table_rden : out STD_LOGIC;
search_table_wren : out STD_LOGIC);
end component esoc_search_engine_sa;
component esoc_search_engine_control
port(
clk_control : in std_logic;
clk_search : in std_logic;
ctrl_address : in std_logic_vector(15 downto 0);
ctrl_rd : in std_logic;
ctrl_rddata : out std_logic_vector(31 downto 0);
ctrl_wait : out std_logic;
ctrl_wr : in std_logic;
ctrl_wrdata : in std_logic_vector(31 downto 0);
reset : in std_logic;
search_entry_age_time : out std_logic_vector(11 downto 0);
search_entry_age_time_ena : out std_logic;
search_sa_drop_cnt : in std_logic;
search_sa_overload_cnt : in std_logic);
end component esoc_search_engine_control;
component esoc_ram_8kx80
port(
address_a : in STD_LOGIC_VECTOR(12 downto 0);
address_b : in STD_LOGIC_VECTOR(12 downto 0);
data_a : in STD_LOGIC_VECTOR(79 downto 0);
data_b : in STD_LOGIC_VECTOR(79 downto 0);
wren_a : in STD_LOGIC := '0';
wren_b : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR(79 downto 0);
q_b : out STD_LOGIC_VECTOR(79 downto 0);
clock : in STD_LOGIC := '1';
rden_a : in STD_LOGIC := '1';
rden_b : in STD_LOGIC := '1');
end component esoc_ram_8kx80;
component esoc_search_engine_sa_store
port(
clk_search : in std_logic;
reset : in std_logic;
search_eof : in std_logic;
search_key : in std_logic_vector(63 downto 0);
search_sa_overload_cnt : out std_logic;
search_sa_store_d : out STD_LOGIC_VECTOR(79 downto 0);
search_sa_store_full : in STD_LOGIC;
search_sa_store_wr : out STD_LOGIC;
search_sof : in std_logic);
end component esoc_search_engine_sa_store;
component esoc_fifo_128x80
port(
aclr : in STD_LOGIC := '0';
data : in STD_LOGIC_VECTOR(79 downto 0);
rdclk : in STD_LOGIC;
rdreq : in STD_LOGIC;
wrclk : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(79 downto 0);
rdempty : out STD_LOGIC;
rdusedw : out STD_LOGIC_VECTOR(6 downto 0);
wrfull : out STD_LOGIC;
wrusedw : out STD_LOGIC_VECTOR(6 downto 0));
end component esoc_fifo_128x80;
component esoc_clk_en_gen
port(
clk : in std_logic;
clk_div : in integer;
clk_en : out std_logic;
reset : in std_logic);
end component esoc_clk_en_gen;
begin
--Destination MAC
--Address Processing
--Source MAC Address
--Processing and aging control
--MAC Address Table
--Search Engine Control
--SA, VID and
--Source port buffer
esoc_clk_en_gen_div <= clk_search_en_div_1s when esoc_mode = normal else clk_search_en_div_1s_sim;
u0: esoc_search_engine_da
port map(
clk_search => clk_search,
reset => reset,
search_eof => search_eof,
search_key => search_key,
search_port_stalled => search_port_stalled,
search_result => search_result,
search_result_av => search_result_av,
search_sof => search_sof,
search_table_address => address_a,
search_table_data => data_a,
search_table_q => q_a,
search_table_rden => Net_0,
search_table_wren => wren_a);
u1: esoc_search_engine_sa
port map(
clk_search => clk_search,
reset => reset,
search_aging_tick => clk_en,
search_entry_age_time => search_entry_age_time,
search_entry_age_time_ena => search_entry_age_time_ena,
search_sa_drop_cnt => search_sa_drop_cnt,
search_sa_store_empty => rdempty,
search_sa_store_q => q,
search_sa_store_rd => rdreq,
search_sa_store_words => rdusedw,
search_table_address => address_b,
search_table_data => data_b,
search_table_q => q_b,
search_table_rden => rden_b,
search_table_wren => sa_wren);
u3: esoc_search_engine_control
port map(
clk_control => clk_control,
clk_search => clk_search,
ctrl_address => ctrl_address,
ctrl_rd => ctrl_rd,
ctrl_rddata => ctrl_rddata,
ctrl_wait => ctrl_wait,
ctrl_wr => ctrl_wr,
ctrl_wrdata => ctrl_wrdata,
reset => reset,
search_entry_age_time => search_entry_age_time,
search_entry_age_time_ena => search_entry_age_time_ena,
search_sa_drop_cnt => search_sa_drop_cnt,
search_sa_overload_cnt => search_sa_overload_cnt);
u2: esoc_ram_8kx80
port map(
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => sa_wren,
q_a => q_a,
q_b => q_b,
clock => clk_search,
rden_a => Net_0,
rden_b => rden_b);
u5: esoc_search_engine_sa_store
port map(
clk_search => clk_search,
reset => reset,
search_eof => search_eof,
search_key => search_key,
search_sa_overload_cnt => search_sa_overload_cnt,
search_sa_store_d => data,
search_sa_store_full => wrfull,
search_sa_store_wr => wrreq,
search_sof => search_sof);
u6: esoc_fifo_128x80
port map(
aclr => reset,
data => data,
rdclk => clk_search,
rdreq => rdreq,
wrclk => clk_search,
wrreq => wrreq,
q => q,
rdempty => rdempty,
rdusedw => rdusedw,
wrfull => wrfull,
wrusedw => open);
u7: esoc_clk_en_gen
port map(
clk => clk_search,
clk_div => esoc_clk_en_gen_div,
clk_en => clk_en,
reset => reset);
end architecture esoc_search ; -- of esoc_search_engine
Error running this command: diff -w -U 5 "" "/tmp/OTLeno"
diff: : No such file or directory