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variable MAC_SOURCE_REPLACE_EN
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variable MAC_TARGET_CHECK_EN
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variable MAC_BROADCAST_FILTER_EN
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variable MAC_TX_FF_DEPTH
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variable MAC_RX_FF_DEPTH
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variable header_data
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source sim/rtl_sim/ncsim_sim/script/run_proc.tcl
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frame .f1
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frame .f2
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text .f1.t1 -width 60 -height 20
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button .f2.b1 -text "Quit" -width 5 -command {exit}
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button .f2.b2 -text "Next" -width 5 -command {module_conf}
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pack .f1 .f2
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pack .f1.t1
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pack .f2.b1 .f2.b2 -side left
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set strings \
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{Hi guys,
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Thanks for your interest about this tri-speed ethernet MAC controller.
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Since this project was created at 25-Nov-2005,I put almost all my free time
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on this project.I am exhausted for this two month's extra work.If you think
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this project is useful,let me know that and i will feel much better.
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To increase the flexibility, some optional modules can be removed from
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the design to reduce area.
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Any problem or bug report please contact me by email:
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gaojon@yahoo.com
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jon
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18-Jan-2006
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}
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.f1.t1 insert end $strings
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proc module_conf {} {
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global MAC_SOURCE_REPLACE_EN
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global MAC_TARGET_CHECK_EN
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global MAC_BROADCAST_FILTER_EN
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global MAC_TX_FF_DEPTH
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global MAC_RX_FF_DEPTH
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global header_data
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if {[catch {open ./rtl/verilog/header.v r} fileid]} {
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puts "Failed open ./rtl/verilog/header.v file\n"
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} else {
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gets $fileid line
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if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set MAC_SOURCE_REPLACE_EN 0
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} else {
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set MAC_SOURCE_REPLACE_EN 1
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}
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lappend header_data $line
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gets $fileid line
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if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set MAC_TARGET_CHECK_EN 0
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} else {
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set MAC_TARGET_CHECK_EN 1
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}
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lappend header_data $line
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gets $fileid line
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if {[lindex $line 0]=="//"} {
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set line [lreplace $line 0 0]
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set MAC_BROADCAST_FILTER_EN 0
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} else {
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set MAC_BROADCAST_FILTER_EN 1
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}
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lappend header_data $line
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gets $fileid line
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set MAC_TX_FF_DEPTH [lindex $line 2]
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lappend header_data $line
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gets $fileid line
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set MAC_RX_FF_DEPTH [lindex $line 2]
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lappend header_data $line
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close $fileid
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}
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destroy .f1 .f2
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frame .f1
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frame .f2
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frame .f1.f1
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frame .f1.f2
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frame .f1.f3
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frame .f1.f4
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frame .f1.f5
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frame .f1.f6
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pack .f1 .f2
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pack .f1.f1 .f1.f2 .f1.f3 .f1.f4 .f1.f5 .f1.f6
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label .f1.f1.lb -text "enable source MAC replace module" -width 30
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checkbutton .f1.f1.cb -variable MAC_SOURCE_REPLACE_EN
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label .f1.f2.lb -text "enable target MAC check module " -width 30
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checkbutton .f1.f2.cb -variable MAC_TARGET_CHECK_EN
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label .f1.f3.lb -text "enable broadcast packet filter module" -width 30
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checkbutton .f1.f3.cb -variable MAC_BROADCAST_FILTER_EN
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label .f1.f4.lb -text "MAC_TX_FF_DEPTH" -width 30
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entry .f1.f4.en -textvariable MAC_TX_FF_DEPTH -width 5
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label .f1.f5.lb -text "MAC_RX_FF_DEPTH" -width 30
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entry .f1.f5.en -textvariable MAC_RX_FF_DEPTH -width 5
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button .f2.b1 -width 10 -text "Save" -command {save_header}
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button .f2.b2 -width 10 -text "Verify" -command {run_sim}
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button .f2.b4 -width 10 -text "Exit" -command {exit}
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pack .f1.f1.cb .f1.f1.lb -side right
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pack .f1.f2.cb .f1.f2.lb -side right
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pack .f1.f3.cb .f1.f3.lb -side right
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pack .f1.f4.en .f1.f4.lb -side right
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pack .f1.f5.en .f1.f5.lb -side right
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pack .f2.b1 .f2.b2 .f2.b4 -side left
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}
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proc save_header {} {
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global MAC_SOURCE_REPLACE_EN
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global MAC_TARGET_CHECK_EN
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global MAC_BROADCAST_FILTER_EN
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global MAC_TX_FF_DEPTH
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global MAC_RX_FF_DEPTH
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global header_data
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if {[catch {open ./rtl/verilog/header.v w} fileid]} {
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puts "Failed open ./rtl/verilog/header.v file\n"
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} else {
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set line [lindex $header_data 0]
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if {$MAC_SOURCE_REPLACE_EN==0} {
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set line [linsert $line 0 "//"]
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}
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puts $fileid $line
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set line [lindex $header_data 1]
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if {$MAC_TARGET_CHECK_EN==0} {
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set line [linsert $line 0 "//"]
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}
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puts $fileid $line
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set line [lindex $header_data 2]
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if {$MAC_BROADCAST_FILTER_EN==0} {
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set line [linsert $line 0 "//"]
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}
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puts $fileid $line
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set line [lindex $header_data 3]
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set line [lreplace $line 2 2 $MAC_TX_FF_DEPTH]
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puts $fileid $line
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set line [lindex $header_data 4]
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set line [lreplace $line 2 2 $MAC_RX_FF_DEPTH]
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puts $fileid $line
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close $fileid
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}
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}
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proc start_verify {} {
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cd sim/rtl_sim/modsim_sim/script
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vish run.tcl
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}
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proc start_syn {} {
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cd syn
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synplify_pro syn.prj
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}
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proc run_sim {} {
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cd sim/rtl_sim/modsim_sim/script/
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run_proc
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}
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No newline at end of file
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