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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Diff between revs 37 and 133

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Rev 37 Rev 133
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.3  2002/01/23 10:28:16  mohor
 
// Link in the header changed.
 
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
// simulation of the few cores in a one joined project.
//
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
Line 278... Line 281...
begin
begin
  if(Reset)
  if(Reset)
    Nvalid <= #Tp 1'b0;
    Nvalid <= #Tp 1'b0;
  else
  else
    begin
    begin
      if(~InProgress & InProgress_q1)
      if(~InProgress_q2 & InProgress_q3)
        begin
        begin
          Nvalid <= #Tp 1'b0;
          Nvalid <= #Tp 1'b0;
        end
        end
      else
      else
        begin
        begin
Line 341... Line 344...
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
 
 
// Busy
// Busy
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3;
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
 
 
 
 
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)

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