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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_register.v] - Diff between revs 136 and 138

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Rev 136 Rev 138
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/08/16 12:33:27  mohor
 
// Parameter ResetValue changed to capital letters.
 
//
// Revision 1.4  2002/02/26 16:18:08  mohor
// Revision 1.4  2002/02/26 16:18:08  mohor
// Reset values are passed to registers through parameters
// Reset values are passed to registers through parameters
//
//
// Revision 1.3  2002/01/23 10:28:16  mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
// Link in the header changed.
Line 69... Line 72...
//
//
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module eth_register(DataIn, DataOut, Write, Clk, Reset);
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
 
 
parameter WIDTH = 8; // default parameter of the register width
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
parameter RESET_VALUE = 0;
 
 
input [WIDTH-1:0] DataIn;
input [WIDTH-1:0] DataIn;
 
 
input Write;
input Write;
input Clk;
input Clk;
input Reset;
input Reset;
 
input SyncReset;
 
 
output [WIDTH-1:0] DataOut;
output [WIDTH-1:0] DataOut;
reg    [WIDTH-1:0] DataOut;
reg    [WIDTH-1:0] DataOut;
 
 
 
 
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always @ (posedge Clk or posedge Reset)
always @ (posedge Clk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    DataOut<=#1 RESET_VALUE;
    DataOut<=#1 RESET_VALUE;
  else
  else
 
  if(SyncReset)
 
    DataOut<=#1 RESET_VALUE;
 
  else
  if(Write)                         // write
  if(Write)                         // write
    DataOut<=#1 DataIn;
    DataOut<=#1 DataIn;
end
end
 
 
 
 

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