OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 148 and 250

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 148 Rev 250
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.7  2002/09/04 18:41:06  mohor
 
// Bug when last byte of destination address was not checked fixed.
 
//
// Revision 1.6  2002/03/20 15:14:11  mohor
// Revision 1.6  2002/03/20 15:14:11  mohor
// When in promiscous mode some frames were not received correctly. Fixed.
// When in promiscous mode some frames were not received correctly. Fixed.
//
//
// Revision 1.5  2002/03/02 21:06:32  mohor
// Revision 1.5  2002/03/02 21:06:32  mohor
// Log info was missing.
// Log info was missing.
Line 62... Line 65...
 
 
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       Multicast, MAC, RxAbort
                       Multicast, MAC, RxAbort, AddressMiss
                      );
                      );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
  input        MRxClk;
  input        MRxClk;
Line 89... Line 92...
  input [47:0] MAC;
  input [47:0] MAC;
  input [1:0]  StateData;
  input [1:0]  StateData;
  input        RxEndFrm;
  input        RxEndFrm;
 
 
  output       RxAbort;
  output       RxAbort;
 
  output       AddressMiss;
 
 
 wire BroadcastOK;
 wire BroadcastOK;
 wire ByteCntEq2;
 wire ByteCntEq2;
 wire ByteCntEq3;
 wire ByteCntEq3;
 wire ByteCntEq4;
 wire ByteCntEq4;
Line 104... Line 107...
 wire [31:0] IntHash;
 wire [31:0] IntHash;
 reg [7:0]  ByteHash;
 reg [7:0]  ByteHash;
 reg MulticastOK;
 reg MulticastOK;
 reg UnicastOK;
 reg UnicastOK;
 reg RxAbort;
 reg RxAbort;
 
 reg AddressMiss;
 
 
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
 
 
assign BroadcastOK = Broadcast & ~r_Bro;
assign BroadcastOK = Broadcast & ~r_Bro;
 
 
Line 124... Line 128...
    RxAbort <= #Tp 1'b1;
    RxAbort <= #Tp 1'b1;
  else
  else
    RxAbort <= #Tp 1'b0;
    RxAbort <= #Tp 1'b0;
end
end
 
 
// Hash Address Check, Multicast
 
 
 
 
// This ff holds the "Address Miss" information that is written to the RX BD status.
 
always @ (posedge MRxClk or posedge Reset)
 
begin
 
  if(Reset)
 
    AddressMiss <= #Tp 1'b0;
 
  else if(ByteCntEq7 & RxCheckEn)
 
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK));
 
end
 
 
 
 
 
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    MulticastOK <= #Tp 1'b0;
    MulticastOK <= #Tp 1'b0;
  else if(RxEndFrm | RxAbort)
  else if(RxEndFrm | RxAbort)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.