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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Diff between revs 250 and 261

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Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.8  2002/11/19 17:34:52  mohor
 
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
 
// that a frame was received because of the promiscous mode.
 
//
// Revision 1.7  2002/09/04 18:41:06  mohor
// Revision 1.7  2002/09/04 18:41:06  mohor
// Bug when last byte of destination address was not checked fixed.
// Bug when last byte of destination address was not checked fixed.
//
//
// Revision 1.6  2002/03/20 15:14:11  mohor
// Revision 1.6  2002/03/20 15:14:11  mohor
// When in promiscous mode some frames were not received correctly. Fixed.
// When in promiscous mode some frames were not received correctly. Fixed.
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module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
                       Multicast, MAC, RxAbort, AddressMiss
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
 
                       ControlFrmAddressOK
                      );
                      );
 
 
parameter Tp = 1;
parameter Tp = 1;
 
 
  input        MRxClk;
  input        MRxClk;
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  input        CrcHashGood;
  input        CrcHashGood;
  input        Multicast;
  input        Multicast;
  input [47:0] MAC;
  input [47:0] MAC;
  input [1:0]  StateData;
  input [1:0]  StateData;
  input        RxEndFrm;
  input        RxEndFrm;
 
  input        PassAll;
 
  input        ControlFrmAddressOK;
 
 
  output       RxAbort;
  output       RxAbort;
  output       AddressMiss;
  output       AddressMiss;
 
 
 wire BroadcastOK;
 wire BroadcastOK;
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always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)
begin
begin
  if(Reset)
  if(Reset)
    AddressMiss <= #Tp 1'b0;
    AddressMiss <= #Tp 1'b0;
  else if(ByteCntEq7 & RxCheckEn)
  else if(ByteCntEq7 & RxCheckEn)
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK));
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
end
 
 
 
 
// Hash Address Check, Multicast
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
always @ (posedge MRxClk or posedge Reset)

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