//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_spram_256x32.v ////
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//// eth_spram_256x32.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is available in the Readme.txt ////
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//// All additional information is available in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/10/10 16:29:30 mohor
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// Revision 1.3 2002/10/10 16:29:30 mohor
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// BIST added.
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// BIST added.
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//
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//
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// Revision 1.2 2002/09/23 18:24:31 mohor
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// Revision 1.2 2002/09/23 18:24:31 mohor
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// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
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// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
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//
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//
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// Revision 1.1 2002/07/23 16:36:09 mohor
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// Revision 1.1 2002/07/23 16:36:09 mohor
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// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
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// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
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//
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//
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_spram_256x32(
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module eth_spram_256x32(
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, rst, ce, we, oe, addr, di, do
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clk, rst, ce, we, oe, addr, di, do
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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scanb_rst, // bist scan reset
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scanb_rst, // bist scan reset
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scanb_clk, // bist scan clock
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scanb_clk, // bist scan clock
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scanb_si, // bist scan serial in
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scanb_si, // bist scan serial in
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scanb_so, // bist scan serial out
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scanb_so, // bist scan serial out
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scanb_en // bist scan shift enable
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scanb_en // bist scan shift enable
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`endif
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`endif
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);
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);
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock, rising edge
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input clk; // Clock, rising edge
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input rst; // Reset, active high
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input rst; // Reset, active high
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input ce; // Chip enable input, active high
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input ce; // Chip enable input, active high
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input we; // Write enable input, active high
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input we; // Write enable input, active high
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input oe; // Output enable input, active high
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input oe; // Output enable input, active high
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input [7:0] addr; // address bus inputs
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input [7:0] addr; // address bus inputs
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input [31:0] di; // input data bus
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input [31:0] di; // input data bus
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output [31:0] do; // output data bus
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output [31:0] do; // output data bus
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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input scanb_rst; // bist scan reset
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input scanb_rst; // bist scan reset
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input scanb_clk; // bist scan clock
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input scanb_clk; // bist scan clock
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input scanb_si; // bist scan serial in
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input scanb_si; // bist scan serial in
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output scanb_so; // bist scan serial out
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output scanb_so; // bist scan serial out
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input scanb_en; // bist scan shift enable
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input scanb_en; // bist scan shift enable
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`endif
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`endif
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`ifdef ETH_XILINX_RAMB4
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`ifdef ETH_XILINX_RAMB4
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RAMB4_S16 ram0
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RAMB4_S16 ram0
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(
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(
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.DO (do[15:0]),
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.DO (do[15:0]),
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.ADDR (addr),
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.ADDR (addr),
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.DI (di[15:0]),
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.DI (di[15:0]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we),
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.WE (we),
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.RST (rst)
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.RST (rst)
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);
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);
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RAMB4_S16 ram1
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RAMB4_S16 ram1
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(
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(
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.DO (do[31:16]),
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.DO (do[31:16]),
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.ADDR (addr),
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.ADDR (addr),
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.DI (di[31:16]),
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.DI (di[31:16]),
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.EN (ce),
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.EN (ce),
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.CLK (clk),
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.CLK (clk),
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.WE (we),
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.WE (we),
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.RST (rst)
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.RST (rst)
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);
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);
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`else // !ETH_XILINX_RAMB4
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`else // !ETH_XILINX_RAMB4
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_VIRTUAL_SILICON_RAM
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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vs_hdsp_256x32_bist ram0_bist
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vs_hdsp_256x32_bist ram0_bist
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`else
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`else
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vs_hdsp_256x32 ram0
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vs_hdsp_256x32 ram0
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`endif
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`endif
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(
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(
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.CK (clk),
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.CK (clk),
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.CEN (!ce),
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.CEN (!ce),
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.WEN (!we),
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.WEN (!we),
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.OEN (!oe),
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.OEN (!oe),
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.ADR (addr),
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.ADR (addr),
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.DI (di),
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.DI (di),
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.DOUT (do)
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.DOUT (do)
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`ifdef ETH_BIST
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`ifdef ETH_BIST
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,
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,
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// debug chain signals
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// debug chain signals
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.scanb_rst (scanb_rst),
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.scanb_rst (scanb_rst),
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.scanb_clk (scanb_clk),
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.scanb_clk (scanb_clk),
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.scanb_si (scanb_si),
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.scanb_si (scanb_si),
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.scanb_so (scanb_so),
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.scanb_so (scanb_so),
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.scanb_en (scanb_en)
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.scanb_en (scanb_en)
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`endif
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`endif
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);
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);
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`else // !ETH_VIRTUAL_SILICON_RAM
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`else // !ETH_VIRTUAL_SILICON_RAM
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//
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//
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// Generic single-port synchronous RAM model
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// Generic single-port synchronous RAM model
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//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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reg [31:0] mem [255:0]; // RAM content
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reg [31:0] mem [255:0]; // RAM content
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wire [31:0] q; // RAM output
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wire [31:0] q; // RAM output
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reg [7:0] raddr; // RAM read address
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reg [7:0] raddr; // RAM read address
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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assign do = (oe & ce) ? q : {32{1'bz}};
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assign do = (oe & ce) ? q : {32{1'bz}};
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//
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//
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// RAM read and write
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// RAM read and write
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//
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//
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// read operation
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// read operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce) // && !we)
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if (ce) // && !we)
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raddr <= #1 addr; // read address needs to be registered to read clock
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raddr <= #1 addr; // read address needs to be registered to read clock
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assign #1 q = rst ? {32{1'b0}} : mem[raddr];
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assign #1 q = rst ? {32{1'b0}} : mem[raddr];
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// write operation
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// write operation
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always@(posedge clk)
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always@(posedge clk)
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if (ce && we)
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if (ce && we)
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mem[addr] <= #1 di;
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mem[addr] <= #1 di;
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// Task prints range of memory
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// Task prints range of memory
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// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
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// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
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task print_ram;
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task print_ram;
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input [7:0] start;
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input [7:0] start;
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input [7:0] finish;
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input [7:0] finish;
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integer rnum;
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integer rnum;
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begin
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begin
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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for (rnum=start;rnum<=finish;rnum=rnum+1)
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$display("Addr %h = %h",rnum,mem[rnum]);
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$display("Addr %h = %h",rnum,mem[rnum]);
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end
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end
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endtask
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endtask
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`endif // !ETH_VIRTUAL_SILICON_RAM
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`endif // !ETH_VIRTUAL_SILICON_RAM
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`endif // !ETH_XILINX_RAMB4
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`endif // !ETH_XILINX_RAMB4
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endmodule
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endmodule
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