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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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//
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// Revision 1.3 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.2 2001/09/11 14:17:00 mohor
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// Revision 1.2 2001/09/11 14:17:00 mohor
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
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ResetCollision
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ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
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LateCollision, StartDefer, StatePreamble, StateData
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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output TxRetry; // Transmit packet retry (to RISC)
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output TxRetry; // Transmit packet retry (to RISC)
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output TxAbort; // Transmit packet abort (to RISC)
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output TxAbort; // Transmit packet abort (to RISC)
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output TxUsedData; // Transmit packet used data (to RISC)
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output TxUsedData; // Transmit packet used data (to RISC)
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output WillTransmit; // Will transmit (to RxEthMAC)
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output WillTransmit; // Will transmit (to RxEthMAC)
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output ResetCollision; // Reset Collision (for synchronizing collision)
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output ResetCollision; // Reset Collision (for synchronizing collision)
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output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
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output StartTxDone;
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output StartTxAbort;
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output MaxCollisionOccured;
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output LateCollision;
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output StartDefer;
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output StatePreamble;
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output [1:0] StateData;
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reg [3:0] MTxD;
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reg [3:0] MTxD;
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reg MTxEn;
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reg MTxEn;
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reg MTxErr;
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reg MTxErr;
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reg TxDone;
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reg TxDone;
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reg [3:0] RetryCnt;
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reg [3:0] RetryCnt;
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reg [3:0] MTxD_d;
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reg [3:0] MTxD_d;
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reg StatusLatch;
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reg StatusLatch;
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reg PacketFinished_q;
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reg PacketFinished_q;
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reg PacketFinished;
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reg PacketFinished;
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reg [3:0] RetryCntLatched;
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wire ExcessiveDeferOccured;
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wire ExcessiveDeferOccured;
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wire StartDefer;
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wire StartIPG;
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wire StartIPG;
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wire StartPreamble;
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wire StartPreamble;
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wire [1:0] StartData;
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wire [1:0] StartData;
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wire StartFCS;
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wire StartFCS;
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wire StartJam;
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wire StartJam;
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wire StartBackoff;
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wire StartBackoff;
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wire StateDefer;
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wire StateDefer;
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wire StateIPG;
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wire StateIPG;
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wire StateIdle;
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wire StateIdle;
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wire StatePreamble;
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wire [1:0] StateData;
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wire StatePAD;
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wire StatePAD;
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wire StateFCS;
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wire StateFCS;
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wire StateJam;
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wire StateJam;
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wire StateBackOff;
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wire StateBackOff;
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wire StateSFD;
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wire StateSFD;
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wire StartTxRetry;
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wire StartTxRetry;
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wire StartTxDone;
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wire LateCollision;
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wire MaxCollisionOccured;
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wire UnderRun;
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wire UnderRun;
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wire TooBig;
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wire TooBig;
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wire StartTxAbort;
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wire [31:0] Crc;
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wire [31:0] Crc;
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wire CrcError;
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wire CrcError;
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wire [2:0] DlyCrcCnt;
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wire [2:0] DlyCrcCnt;
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wire [15:0] NibCnt;
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wire [15:0] NibCnt;
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wire NibCntEq7;
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wire NibCntEq7;
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