| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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//
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//
|
// CVS Revision History
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// CVS Revision History
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//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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|
// Revision 1.33 2002/09/04 18:47:57 mohor
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// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
|
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// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
|
|
// was not used OK.
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//
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// Revision 1.32 2002/08/14 19:31:48 mohor
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// Revision 1.32 2002/08/14 19:31:48 mohor
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// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
|
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
|
// need to multiply or devide any more.
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// need to multiply or devide any more.
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//
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//
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// Revision 1.31 2002/07/25 18:29:01 mohor
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// Revision 1.31 2002/07/25 18:29:01 mohor
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| Line 147... |
Line 152... |
// Revision 1.1 2002/01/23 10:47:59 mohor
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// Revision 1.1 2002/01/23 10:47:59 mohor
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// Initial version. Equals to eth_wishbonedma.v at this moment.
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// Initial version. Equals to eth_wishbonedma.v at this moment.
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//
|
//
|
//
|
//
|
//
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//
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//
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|
|
|
// Build pause frame
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|
// Check GotData and evaluate data (abort or something like that comes before StartFrm)
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// m_wb_err_i should start status underrun or uverrun
|
|
// r_RecSmall not used
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|
|
|
`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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| Line 346... |
Line 345... |
reg TxRetry_q;
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reg TxRetry_q;
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reg TxUsedData_q;
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reg TxUsedData_q;
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|
|
reg [31:0] RxDataLatched2;
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reg [31:0] RxDataLatched2;
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|
|
// reg [23:0] RxDataLatched1;
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reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
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reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
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|
|
reg [1:0] RxValidBytes;
|
reg [1:0] RxValidBytes;
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reg [1:0] RxByteCnt;
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reg [1:0] RxByteCnt;
|
reg LastByteIn;
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reg LastByteIn;
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| Line 418... |
Line 416... |
|
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wire StartRxPointerRead;
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wire StartRxPointerRead;
|
reg RxPointerRead;
|
reg RxPointerRead;
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I)
|
begin
|
|
if(Reset)
|
|
begin
|
|
WB_ACK_O <=#Tp 1'b0;
|
|
end
|
|
else
|
|
begin
|
begin
|
WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
WB_ACK_O <=#Tp BDWrite & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
|
end
|
end
|
end
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|
|
|
assign WB_DAT_O = ram_do;
|
assign WB_DAT_O = ram_do;
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|
|
// Generic synchronous single-port RAM interface
|
// Generic synchronous single-port RAM interface
|
eth_spram_256x32 bd_ram (
|
eth_spram_256x32 bd_ram (
|
// Generic synchronous single-port RAM interface
|
|
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
|
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
|
);
|
);
|
|
|
assign ram_ce = 1'b1;
|
assign ram_ce = 1'b1;
|
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
|
assign ram_we = BDWrite & WbEn & WbEn_q | TxStatusWrite | RxStatusWrite;
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| Line 634... |
Line 624... |
if(~TxDone_wb & ~TxAbort_wb)
|
if(~TxDone_wb & ~TxAbort_wb)
|
BlockingTxStatusWrite <=#Tp 1'b0;
|
BlockingTxStatusWrite <=#Tp 1'b0;
|
end
|
end
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|
|
|
|
|
reg BlockingTxStatusWrite_sync1;
|
|
reg BlockingTxStatusWrite_sync2;
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|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
|
|
end
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
|
|
else
|
|
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
|
|
end
|
|
|
|
|
// TxBDRead state is activated only once.
|
// TxBDRead state is activated only once.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
BlockingTxBDRead <=#Tp 1'b0;
|
BlockingTxBDRead <=#Tp 1'b0;
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| Line 675... |
Line 687... |
|
|
wire TxLengthEq0;
|
wire TxLengthEq0;
|
wire TxLengthLt4;
|
wire TxLengthLt4;
|
|
|
reg BlockingIncrementTxPointer;
|
reg BlockingIncrementTxPointer;
|
reg [31:0] TxPointer;
|
reg [31:2] TxPointerMSB;
|
reg [1:0] TxPointerLatched;
|
reg [1:0] TxPointerLSB;
|
reg [1:0] TxPointerLatched_rst;
|
reg [1:0] TxPointerLSB_rst;
|
reg [31:0] RxPointer;
|
reg [31:2] RxPointerMSB;
|
reg [1:0] RxPointerLatched;
|
reg [1:0] RxPointerLSB_rst;
|
|
|
wire RxBurstAcc;
|
wire RxBurstAcc;
|
wire RxWordAcc;
|
wire RxWordAcc;
|
wire RxHalfAcc;
|
wire RxHalfAcc;
|
wire RxByteAcc;
|
wire RxByteAcc;
|
| Line 700... |
Line 712... |
if(MasterWbTX & m_wb_ack_i)
|
if(MasterWbTX & m_wb_ack_i)
|
begin
|
begin
|
if(TxLengthLt4)
|
if(TxLengthLt4)
|
TxLength <=#Tp 16'h0;
|
TxLength <=#Tp 16'h0;
|
else
|
else
|
if(TxPointerLatched_rst==2'h0)
|
if(TxPointerLSB_rst==2'h0)
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLatched_rst==2'h1)
|
if(TxPointerLSB_rst==2'h1)
|
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLatched_rst==2'h2)
|
if(TxPointerLSB_rst==2'h2)
|
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
|
else
|
else
|
if(TxPointerLatched_rst==2'h3)
|
if(TxPointerLSB_rst==2'h3)
|
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
|
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
|
end
|
end
|
end
|
end
|
|
|
|
|
| Line 733... |
Line 745... |
|
|
reg cyc_cleared;
|
reg cyc_cleared;
|
reg IncrTxPointer;
|
reg IncrTxPointer;
|
|
|
|
|
//Latching Tx buffer pointer from buffer descriptor;
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
|
|
// because TxPointerMSB is only used for word-aligned accesses.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointer <=#Tp 0;
|
TxPointerMSB <=#Tp 30'h0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointer <=#Tp ram_do;
|
TxPointerMSB <=#Tp ram_do[31:2];
|
else
|
else
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
if(IncrTxPointer & ~BlockingIncrementTxPointer)
|
TxPointer <=#Tp TxPointer + 3'h4; // Word access
|
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
|
|
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
|
|
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
|
|
// set by this two bits.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLatched[1:0] <=#Tp 0;
|
TxPointerLSB[1:0] <=#Tp 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLatched[1:0] <=#Tp ram_do[1:0];
|
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
// Latching 2 MSB bits of the buffer descriptor.
|
|
// After the read access, TxLength needs to be decremented for the number of the valid
|
|
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
|
|
// valid so this two bits are reset to zero.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxPointerLatched_rst[1:0] <=#Tp 0;
|
TxPointerLSB_rst[1:0] <=#Tp 0;
|
else
|
else
|
if(TxEn & TxEn_q & TxPointerRead)
|
if(TxEn & TxEn_q & TxPointerRead)
|
TxPointerLatched_rst[1:0] <=#Tp ram_do[1:0];
|
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
|
else
|
else
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
|
TxPointerLatched_rst[1:0] <=#Tp 0;
|
TxPointerLSB_rst[1:0] <=#Tp 0;
|
end
|
end
|
|
|
|
|
reg [3:0] m_wb_sel_tmp_rx;
|
reg [3:0] RxByteSel;
|
wire MasterAccessFinished;
|
wire MasterAccessFinished;
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
| Line 832... |
Line 851... |
end
|
end
|
|
|
|
|
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
|
reg [3:0] state;
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
state <=#Tp 4'h0;
|
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbTX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_adr_o <=#Tp 32'h0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
| Line 855... |
Line 873... |
begin
|
begin
|
// Switching between two stages depends on enable signals
|
// Switching between two stages depends on enable signals
|
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared}) // synopsys parallel_case
|
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared}) // synopsys parallel_case
|
6'b00_01_0_x, 6'b00_11_0_x :
|
6'b00_01_0_x, 6'b00_11_0_x :
|
begin
|
begin
|
state <=#Tp 4'h1;
|
|
MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // idle and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp RxByteSel;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b00_10_0_x, 6'b00_10_1_x :
|
6'b00_10_0_x, 6'b00_10_1_x :
|
begin
|
begin
|
state <=#Tp 4'h2;
|
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // idle and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b10_10_0_1 :
|
6'b10_10_0_1 :
|
begin
|
begin
|
state <=#Tp 4'h3;
|
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master read and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b01_01_0_1 :
|
6'b01_01_0_1 :
|
begin
|
begin
|
state <=#Tp 4'h4;
|
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master write and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp RxByteSel;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_01_0_1, 6'b10_11_0_1 :
|
6'b10_01_0_1, 6'b10_11_0_1 :
|
begin
|
begin
|
state <=#Tp 4'h5;
|
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbTX <=#Tp 1'b0; // master read and master write is needed (data write to rx buffer)
|
MasterWbRX <=#Tp 1'b1;
|
MasterWbRX <=#Tp 1'b1;
|
m_wb_adr_o <=#Tp RxPointer;
|
m_wb_adr_o <=#Tp {RxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b1;
|
m_wb_sel_o <=#Tp m_wb_sel_tmp_rx;
|
m_wb_sel_o <=#Tp RxByteSel;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b01_10_0_1, 6'b01_11_0_1 :
|
6'b01_10_0_1, 6'b01_11_0_1 :
|
begin
|
begin
|
state <=#Tp 4'h6;
|
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbTX <=#Tp 1'b1; // master write and master read is needed (data read from tx buffer)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_adr_o <=#Tp {TxPointer[31:2], 2'h0};
|
m_wb_adr_o <=#Tp {TxPointerMSB, 2'h0};
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_cyc_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_stb_o <=#Tp 1'b1;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_we_o <=#Tp 1'b0;
|
m_wb_sel_o <=#Tp 4'hf;
|
m_wb_sel_o <=#Tp 4'hf;
|
cyc_cleared<=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b1;
|
end
|
end
|
6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
|
6'b10_10_1_0, 6'b01_01_1_0, 6'b10_01_1_0, 6'b10_11_1_0, 6'b01_10_1_0, 6'b01_11_1_0 :
|
begin
|
begin
|
state <=#Tp 4'h7;
|
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
cyc_cleared<=#Tp 1'b1;
|
cyc_cleared<=#Tp 1'b1;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_00_1_x, 6'b01_00_1_x :
|
6'b10_00_1_x, 6'b01_00_1_x :
|
begin
|
begin
|
state <=#Tp 4'h8;
|
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbTX <=#Tp 1'b0; // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
end
|
end
|
6'b10_00_0_1, 6'b01_00_0_1 :
|
6'b10_00_0_1, 6'b01_00_0_1 :
|
begin
|
begin
|
state <=#Tp 4'h9;
|
|
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
|
MasterWbTX <=#Tp 1'b0; // Between cyc_cleared request was cleared
|
MasterWbRX <=#Tp 1'b0;
|
MasterWbRX <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_cyc_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
m_wb_stb_o <=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
IncrTxPointer<=#Tp 1'b0;
|
| Line 1268... |
Line 1277... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxData <=#Tp 0;
|
TxData <=#Tp 0;
|
else
|
else
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
if(TxStartFrm_sync2 & ~TxStartFrm)
|
case(TxPointerLatched) // synopsys parallel_case
|
case(TxPointerLSB) // synopsys parallel_case
|
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
|
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
|
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
|
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
|
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
|
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
|
endcase
|
endcase
|
else
|
else
|
if(TxStartFrm & TxUsedData & TxPointerLatched==2'h3)
|
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
|
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
begin
|
begin
|
case(TxByteCnt) // synopsys parallel_case
|
case(TxByteCnt) // synopsys parallel_case
|
| Line 1315... |
Line 1324... |
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
|
TxUnderRun_wb <=#Tp 1'b1;
|
TxUnderRun_wb <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
reg TxUnderRun_sync1;
|
|
|
// Tx under run
|
// Tx under run
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun_sync1 <=#Tp 1'b0;
|
else
|
else
|
if(TxUnderRun_wb)
|
if(TxUnderRun_wb)
|
TxUnderRun <=#Tp 1'b1;
|
TxUnderRun_sync1 <=#Tp 1'b1;
|
|
else
|
|
if(BlockingTxStatusWrite_sync2)
|
|
TxUnderRun_sync1 <=#Tp 1'b0;
|
|
end
|
|
|
|
// Tx under run
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
TxUnderRun <=#Tp 1'b0;
|
else
|
else
|
if(BlockingTxStatusWrite)
|
if(BlockingTxStatusWrite_sync2)
|
TxUnderRun <=#Tp 1'b0;
|
TxUnderRun <=#Tp 1'b0;
|
|
else
|
|
if(TxUnderRun_sync1)
|
|
TxUnderRun <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Tx Byte counter
|
// Tx Byte counter
|
always @ (posedge MTxClk or posedge Reset)
|
always @ (posedge MTxClk or posedge Reset)
|
| Line 1339... |
Line 1363... |
else
|
else
|
if(TxAbort_q | TxRetry_q)
|
if(TxAbort_q | TxRetry_q)
|
TxByteCnt <=#Tp 2'h0;
|
TxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(TxStartFrm & ~TxUsedData)
|
if(TxStartFrm & ~TxUsedData)
|
case(TxPointerLatched) // synopsys parallel_case
|
case(TxPointerLSB) // synopsys parallel_case
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
2'h0 : TxByteCnt <=#Tp 2'h1;
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
2'h1 : TxByteCnt <=#Tp 2'h2;
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
2'h2 : TxByteCnt <=#Tp 2'h3;
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
2'h3 : TxByteCnt <=#Tp 2'h0;
|
endcase
|
endcase
|
else
|
else
|
if(TxUsedData & Flop)
|
if(TxUsedData & Flop)
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
TxByteCnt <=#Tp TxByteCnt + 1'b1;
|
end
|
end
|
|
|
/*
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
reg ReadTxDataFromFifo_sync1;
|
|
reg ReadTxDataFromFifo_sync2;
|
|
reg ReadTxDataFromFifo_sync3;
|
|
reg ReadTxDataFromFifo_syncb1;
|
|
reg ReadTxDataFromFifo_syncb2;
|
|
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
|
else
|
|
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b1;
|
|
else
|
|
if(ReadTxDataFromFifo_syncb2)
|
|
ReadTxDataFromFifo_tck <=#Tp 1'b0;
|
|
end
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
|
|
else
|
|
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
|
|
end
|
|
|
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
|
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
*/
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync1;
|
reg ReadTxDataFromFifo_sync2;
|
reg ReadTxDataFromFifo_sync2;
|
reg ReadTxDataFromFifo_sync3;
|
reg ReadTxDataFromFifo_sync3;
|
| Line 1620... |
Line 1579... |
|
|
//Latching Rx buffer pointer from buffer descriptor;
|
//Latching Rx buffer pointer from buffer descriptor;
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointer <=#Tp 32'h0;
|
RxPointerMSB <=#Tp 30'h0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointer <=#Tp {ram_do[31:2], 2'h0};
|
RxPointerMSB <=#Tp ram_do[31:2];
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i)
|
if(MasterWbRX & m_wb_ack_i)
|
RxPointer <=#Tp RxPointer + 3'h4; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
RxPointerMSB <=#Tp RxPointerMSB + 1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
end
|
end
|
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxPointerLatched[1:0] <=#Tp 0;
|
RxPointerLSB_rst[1:0] <=#Tp 0;
|
else
|
else
|
if(MasterWbRX & m_wb_ack_i) // After first write all m_wb_sel_tmp_rx are active
|
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
|
RxPointerLatched[1:0] <=#Tp 0;
|
RxPointerLSB_rst[1:0] <=#Tp 0;
|
else
|
else
|
if(RxEn & RxEn_q & RxPointerRead)
|
if(RxEn & RxEn_q & RxPointerRead)
|
RxPointerLatched[1:0] <=#Tp ram_do[1:0];
|
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
|
end
|
end
|
|
|
|
|
always @ (RxPointerLatched)
|
always @ (RxPointerLSB_rst)
|
begin
|
begin
|
case(RxPointerLatched[1:0]) // synopsys parallel_case
|
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
|
2'h0 : m_wb_sel_tmp_rx[3:0] = 4'hf;
|
2'h0 : RxByteSel[3:0] = 4'hf;
|
2'h1 : m_wb_sel_tmp_rx[3:0] = 4'h7;
|
2'h1 : RxByteSel[3:0] = 4'h7;
|
2'h2 : m_wb_sel_tmp_rx[3:0] = 4'h3;
|
2'h2 : RxByteSel[3:0] = 4'h3;
|
2'h3 : m_wb_sel_tmp_rx[3:0] = 4'h1;
|
2'h3 : RxByteSel[3:0] = 4'h1;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
| Line 1714... |
Line 1673... |
else
|
else
|
if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
if(RxValid & RxBDReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
|
LastByteIn <=#Tp 1'b1;
|
LastByteIn <=#Tp 1'b1;
|
end
|
end
|
|
|
reg ShiftEnded_tck;
|
reg ShiftEnded_rck;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync1;
|
reg ShiftEndedSync2;
|
reg ShiftEndedSync2;
|
reg ShiftEndedSync3;
|
reg ShiftEndedSync3;
|
reg ShiftEndedSync_c1;
|
reg ShiftEndedSync_c1;
|
reg ShiftEndedSync_c2;
|
reg ShiftEndedSync_c2;
|
|
|
wire StartShiftWillEnd;
|
wire StartShiftWillEnd;
|
//assign StartShiftWillEnd = LastByteIn & (&RxByteCnt) | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
|
|
|
// Indicating that data reception will end
|
// Indicating that data reception will end
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftWillEnd <=#Tp 1'b0;
|
ShiftWillEnd <=#Tp 1'b0;
|
else
|
else
|
if(ShiftEnded_tck | RxAbort)
|
if(ShiftEnded_rck | RxAbort)
|
ShiftWillEnd <=#Tp 1'b0;
|
ShiftWillEnd <=#Tp 1'b0;
|
else
|
else
|
if(StartShiftWillEnd)
|
if(StartShiftWillEnd)
|
ShiftWillEnd <=#Tp 1'b1;
|
ShiftWillEnd <=#Tp 1'b1;
|
end
|
end
|
| Line 1746... |
Line 1704... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(ShiftEnded_tck | RxAbort)
|
if(ShiftEnded_rck | RxAbort)
|
RxByteCnt <=#Tp 2'h0;
|
RxByteCnt <=#Tp 2'h0;
|
else
|
else
|
if(RxValid & RxStartFrm & RxBDReady)
|
if(RxValid & RxStartFrm & RxBDReady)
|
case(RxPointerLatched) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
2'h0 : RxByteCnt <=#Tp 2'h1;
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
2'h1 : RxByteCnt <=#Tp 2'h2;
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
2'h2 : RxByteCnt <=#Tp 2'h3;
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
2'h3 : RxByteCnt <=#Tp 2'h0;
|
endcase
|
endcase
|
| Line 1769... |
Line 1727... |
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxValidBytes <=#Tp 2'h1;
|
RxValidBytes <=#Tp 2'h1;
|
else
|
else
|
if(RxValid & RxStartFrm)
|
if(RxValid & RxStartFrm)
|
case(RxPointerLatched) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
2'h0 : RxValidBytes <=#Tp 2'h1;
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
2'h1 : RxValidBytes <=#Tp 2'h2;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h2 : RxValidBytes <=#Tp 2'h3;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
2'h3 : RxValidBytes <=#Tp 2'h0;
|
endcase
|
endcase
|
| Line 1789... |
Line 1747... |
RxDataLatched1 <=#Tp 24'h0;
|
RxDataLatched1 <=#Tp 24'h0;
|
else
|
else
|
if(RxValid & RxBDReady & ~LastByteIn)
|
if(RxValid & RxBDReady & ~LastByteIn)
|
if(RxStartFrm)
|
if(RxStartFrm)
|
begin
|
begin
|
case(RxPointerLatched) // synopsys parallel_case
|
case(RxPointerLSB_rst) // synopsys parallel_case
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
|
endcase
|
endcase
|
| Line 1820... |
Line 1778... |
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
else
|
else
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
if(SetWriteRxDataToFifo & ShiftWillEnd)
|
case(RxValidBytes) // synopsys parallel_case
|
case(RxValidBytes) // synopsys parallel_case
|
// 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
|
// 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
|
// 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
|
// 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
|
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
|
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
|
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
|
endcase
|
endcase
|
| Line 1838... |
Line 1792... |
reg WriteRxDataToFifoSync2;
|
reg WriteRxDataToFifoSync2;
|
reg WriteRxDataToFifoSync3;
|
reg WriteRxDataToFifoSync3;
|
|
|
|
|
// Indicating start of the reception process
|
// Indicating start of the reception process
|
//assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLSB_rst)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
assign SetWriteRxDataToFifo = (RxValid & RxBDReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | (RxValid & RxBDReady & RxStartFrm & (&RxPointerLatched)) | (ShiftWillEnd & LastByteIn & (&RxByteCnt));
|
|
/*
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifo <=#Tp 1'b0;
|
|
else
|
|
if(SetWriteRxDataToFifo & ~RxAbort)
|
|
WriteRxDataToFifo <=#Tp 1'b1;
|
|
else
|
|
if(WriteRxDataToFifoSync1 | RxAbort)
|
|
WriteRxDataToFifo <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
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|
else
|
|
if(WriteRxDataToFifo)
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b1;
|
|
else
|
|
WriteRxDataToFifoSync1 <=#Tp 1'b0;
|
|
end
|
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
WriteRxDataToFifoSync2 <=#Tp 1'b0;
|
|
else
|
|
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
|
|
end
|
|
|
|
wire WriteRxDataToFifo_wb;
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|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync1 & ~WriteRxDataToFifoSync2;
|
|
*/
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
WriteRxDataToFifo <=#Tp 1'b0;
|
WriteRxDataToFifo <=#Tp 1'b0;
|
| Line 1992... |
Line 1908... |
|
|
// Generation of the end-of-frame signal
|
// Generation of the end-of-frame signal
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_rck <=#Tp 1'b0;
|
else
|
else
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
|
ShiftEnded_tck <=#Tp 1'b1;
|
ShiftEnded_rck <=#Tp 1'b1;
|
else
|
else
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
|
ShiftEnded_tck <=#Tp 1'b0;
|
ShiftEnded_rck <=#Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShiftEndedSync1 <=#Tp 1'b0;
|
ShiftEndedSync1 <=#Tp 1'b0;
|
else
|
else
|
ShiftEndedSync1 <=#Tp ShiftEnded_tck;
|
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
|
end
|
end
|
|
|
always @ (posedge WB_CLK_I or posedge Reset)
|
always @ (posedge WB_CLK_I or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
| Line 2134... |
Line 2050... |
else
|
else
|
if(RxAbort)
|
if(RxAbort)
|
RxAbortLatched <=#Tp 1'b1;
|
RxAbortLatched <=#Tp 1'b1;
|
end
|
end
|
|
|
/*
|
|
reg LoadStatusBlocked;
|
|
|
|
always @ (posedge MRxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LoadStatusBlocked <=#Tp 1'b0;
|
|
else
|
|
if(LoadRxStatus & ~RxAbortLatched)
|
|
LoadStatusBlocked <=#Tp 1'b1;
|
|
else
|
|
if(RxStatusWrite_rck | RxStartFrm)
|
|
LoadStatusBlocked <=#Tp 1'b0;
|
|
end
|
|
*/
|
|
// LatchedRxLength[15:0]
|
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedRxLength[15:0] <=#Tp 16'h0;
|
LatchedRxLength[15:0] <=#Tp 16'h0;
|
else
|
else
|
// if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
|
end
|
end
|
|
|
|
|
| Line 2168... |
Line 2068... |
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxStatusInLatched <=#Tp 'h0;
|
RxStatusInLatched <=#Tp 'h0;
|
else
|
else
|
// if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
|
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
RxStatusInLatched <=#Tp RxStatusIn;
|
RxStatusInLatched <=#Tp RxStatusIn;
|
end
|
end
|
|
|
|
|
| Line 2287... |
Line 2186... |
// bit 3 od rx je ReceivedPacketTooBig
|
// bit 3 od rx je ReceivedPacketTooBig
|
// bit 2 od rx je ShortFrame
|
// bit 2 od rx je ShortFrame
|
// bit 1 od rx je LatchedCrcError
|
// bit 1 od rx je LatchedCrcError
|
// bit 0 od rx je RxLateCollision
|
// bit 0 od rx je RxLateCollision
|
|
|
assign reg1 = RxPointer[31:0]; /* 0x58 */
|
assign reg1 = {RxPointerMSB[31:2], 2'h0}; /* 0x58 */
|
|
|
assign reg2 = { /* 0x5c */
|
assign reg2 = { /* 0x5c */
|
RxStatusWriteLatched, // 31
|
RxStatusWriteLatched, // 31
|
RxStatusWrite_rck, // 30
|
RxStatusWrite_rck, // 30
|
RxEn_needed, // 29
|
RxEn_needed, // 29
|
| Line 2303... |
Line 2202... |
ShiftEnded, // 23
|
ShiftEnded, // 23
|
RxPointerRead, // 23
|
RxPointerRead, // 23
|
LastByteIn, // 21
|
LastByteIn, // 21
|
ShiftWillEnd, // 20
|
ShiftWillEnd, // 20
|
2'h0, RxByteCnt[1:0], // 19:16
|
2'h0, RxByteCnt[1:0], // 19:16
|
2'h0, RxPointerLatched[1:0], // 15:12
|
2'h0, RxPointerLSB_rst[1:0], // 15:12
|
RxBDAddress[7:0], // 11:4
|
RxBDAddress[7:0], // 11:4
|
state[3:0] // 3:0
|
4'h0 // 3:0
|
};
|
};
|
|
|
assign reg3 = { /* 0x60 */
|
assign reg3 = { /* 0x60 */
|
ShiftEndedSync_c2, // 31
|
ShiftEndedSync_c2, // 31
|
RxAbortSyncb1, // 30
|
RxAbortSyncb1, // 30
|
| Line 2324... |
Line 2223... |
RxValid, // 23
|
RxValid, // 23
|
RxEndFrm, // 22
|
RxEndFrm, // 22
|
RxEnableWindow, // 21
|
RxEnableWindow, // 21
|
StartShiftWillEnd, // 20
|
StartShiftWillEnd, // 20
|
ShiftWillEnd, // 19
|
ShiftWillEnd, // 19
|
ShiftEnded_tck, // 18
|
ShiftEnded_rck, // 18
|
SetWriteRxDataToFifo, // 17
|
SetWriteRxDataToFifo, // 17
|
WriteRxDataToFifo, // 16
|
WriteRxDataToFifo, // 16
|
WriteRxDataToFifoSync3, // 15
|
WriteRxDataToFifoSync3, // 15
|
WriteRxDataToFifoSync2, // 14
|
WriteRxDataToFifoSync2, // 14
|
WriteRxDataToFifoSync1, // 13
|
WriteRxDataToFifoSync1, // 13
|
