| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.44 2002/11/13 22:21:40 tadejm
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// RxError is not generated when small frame reception is enabled and small
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// frames are received.
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//
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// Revision 1.43 2002/10/18 20:53:34 mohor
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// Revision 1.43 2002/10/18 20:53:34 mohor
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// case changed to casex.
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// case changed to casex.
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//
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//
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// Revision 1.42 2002/10/18 17:04:20 tadejm
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// Revision 1.42 2002/10/18 17:04:20 tadejm
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// Changed BIST scan signals.
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// Changed BIST scan signals.
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| Line 233... |
Line 237... |
// Interrupts
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// Interrupts
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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// Rx Status
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// Rx Status
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
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ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
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// Tx Status
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// Tx Status
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
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// Bist
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// Bist
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| Line 297... |
Line 301... |
input DribbleNibble; // Extra nibble received
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input DribbleNibble; // Extra nibble received
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input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
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input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
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input [15:0] RxLength; // Length of the incoming frame
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input [15:0] RxLength; // Length of the incoming frame
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input LoadRxStatus; // Rx status was loaded
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input LoadRxStatus; // Rx status was loaded
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input ReceivedPacketGood;// Received packet's length and CRC are good
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input ReceivedPacketGood;// Received packet's length and CRC are good
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input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
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// Tx Status signals
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// Tx Status signals
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input [3:0] RetryCntLatched; // Latched Retry Counter
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
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input LateCollLatched; // Late collision occured
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input LateCollLatched; // Late collision occured
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| Line 461... |
Line 466... |
wire SetGotData;
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wire SetGotData;
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wire GotDataEvaluate;
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wire GotDataEvaluate;
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reg WB_ACK_O;
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reg WB_ACK_O;
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wire [6:0] RxStatusIn;
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wire [7:0] RxStatusIn;
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reg [6:0] RxStatusInLatched;
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reg [7:0] RxStatusInLatched;
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reg WbEn, WbEn_q;
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reg WbEn, WbEn_q;
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reg RxEn, RxEn_q;
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reg RxEn, RxEn_q;
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reg TxEn, TxEn_q;
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reg TxEn, TxEn_q;
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Line 1346... |
RxBDAddress <=#Tp TempRxBDAddress;
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RxBDAddress <=#Tp TempRxBDAddress;
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end
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end
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 6'h0, RxStatusInLatched};
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assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 5'h0, RxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
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// Signals used for various purposes
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// Signals used for various purposes
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
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| Line 2357... |
Line 2362... |
if(LoadRxStatus)
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if(LoadRxStatus)
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LatchedRxLength[15:0] <=#Tp RxLength[15:0];
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LatchedRxLength[15:0] <=#Tp RxLength[15:0];
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end
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end
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assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
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assign RxStatusIn = {AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
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always @ (posedge MRxClk or posedge Reset)
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always @ (posedge MRxClk or posedge Reset)
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begin
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begin
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if(Reset)
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if(Reset)
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RxStatusInLatched <=#Tp 'h0;
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RxStatusInLatched <=#Tp 'h0;
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| Line 2391... |
Line 2396... |
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wire RxError;
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wire RxError;
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// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
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// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
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// are aborted when signal r_RecSmall is set to 0 in MODER register.
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// are aborted when signal r_RecSmall is set to 0 in MODER register.
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// AddressMiss is identifying that a frame was received because of the promiscous
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// mode and is not an error
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assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
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assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
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// Tx Done Interrupt
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// Tx Done Interrupt
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always @ (posedge WB_CLK_I or posedge Reset)
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always @ (posedge WB_CLK_I or posedge Reset)
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begin
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begin
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