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[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] [eth_top.v] - Diff between revs 202 and 210

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Rev 202 Rev 210
Line 39... Line 39...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.32  2002/09/20 17:12:58  mohor
 
// CsMiss added. When address between 0x800 and 0xfff is accessed within
 
// Ethernet Core, error acknowledge is generated.
 
//
// Revision 1.31  2002/09/12 14:50:17  mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
//
// Revision 1.30  2002/09/10 10:35:23  mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
// Ethernet debug registers removed.
// Ethernet debug registers removed.
Line 191... Line 195...
  // MIIM
  // MIIM
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
 
 
  int_o
  int_o
 
 
 
  // Bist
 
`ifdef ETH_BIST
 
  , trst, SO, SI, shift_DR, capture_DR, extest, tck
 
`endif
 
 
);
);
 
 
 
 
parameter Tp = 1;
parameter Tp = 1;
Line 249... Line 257...
output          md_pad_o;      // MII data output (to I/O cell)
output          md_pad_o;      // MII data output (to I/O cell)
output          md_padoe_o;    // MII data output enable (to I/O cell)
output          md_padoe_o;    // MII data output enable (to I/O cell)
 
 
output          int_o;         // Interrupt output
output          int_o;         // Interrupt output
 
 
 
// Bist
 
`ifdef ETH_BIST
 
input           trst;
 
input           shift_DR, capture_DR, tck, extest;
 
input           SI;
 
output          SO;
 
`endif
 
 
wire     [7:0]  r_ClkDiv;
wire     [7:0]  r_ClkDiv;
wire            r_MiiNoPre;
wire            r_MiiNoPre;
wire    [15:0]  r_CtrlData;
wire    [15:0]  r_CtrlData;
wire     [4:0]  r_FIAD;
wire     [4:0]  r_FIAD;
wire     [4:0]  r_RGAD;
wire     [4:0]  r_RGAD;
Line 718... Line 734...
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood)
 
 
 
`ifdef ETH_BIST
 
  ,
 
  .trst(trst),                        .SO(SO),                                  .SI(SI),
 
  .shift_DR(.shift_DR),               .capture_DR(capture_DR),                  .extest(extest),
 
  .tck(tck)
 
`endif
);
);
 
 
 
 
 
 
// Connecting MacStatus module
// Connecting MacStatus module

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