| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.36 2002/10/18 17:04:20 tadejm
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// Changed BIST scan signals.
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//
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// Revision 1.35 2002/10/11 13:36:58 mohor
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// Revision 1.35 2002/10/11 13:36:58 mohor
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// Typo error fixed. (When using Bist)
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// Typo error fixed. (When using Bist)
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//
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//
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// Revision 1.34 2002/10/10 16:49:50 mohor
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// Revision 1.34 2002/10/10 16:49:50 mohor
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// Signals for WISHBONE B3 compliant interface added.
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// Signals for WISHBONE B3 compliant interface added.
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| Line 406... |
Line 409... |
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10]; // 0x0 - 0x3FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10]; // 0x400 - 0x7FF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11]; // 0x800 - 0xfFF
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_ack_o = RegCs | BDAck;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
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//assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | BDCs & r_Rst | CsMiss);
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assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
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`ifdef ETH_REGISTERED_OUTPUTS
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`ifdef ETH_REGISTERED_OUTPUTS
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_ack_o = temp_wb_ack_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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assign wb_err_o = temp_wb_err_o_reg;
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| Line 511... |
Line 515... |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
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.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
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.PassAll(r_PassAll), .TxFlow(r_TxFlow),
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.PassAll(r_PassAll), .TxFlow(r_TxFlow),
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.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
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.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
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.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
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.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
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.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
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.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
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.CrcEnOut(CrcEnOut), .TxReset(r_Rst),
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.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
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.RxReset(r_Rst), .ReceivedLengthOK(ReceivedLengthOK),
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.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
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.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
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.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
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.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
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.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
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.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
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.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
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.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
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.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
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.ReceivedPauseFrm(ReceivedPauseFrm)
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.ReceivedPauseFrm(ReceivedPauseFrm)
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| Line 552... |
Line 556... |
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// Connecting TxEthMAC
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// Connecting TxEthMAC
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eth_txethmac txethmac1
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eth_txethmac txethmac1
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(
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(
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.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
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.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
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.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
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.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
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.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
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.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
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.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
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.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
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.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
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.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
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.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
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.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
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| Line 588... |
Line 592... |
// Connecting RxEthMAC
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// Connecting RxEthMAC
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eth_rxethmac rxethmac1
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eth_rxethmac rxethmac1
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(
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(
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.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
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.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
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.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
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.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
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.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
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.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
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.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
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.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
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.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
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.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
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.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
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.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
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.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
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.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
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.StateSFD(RxStateSFD), .StateData(RxStateData),
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.StateSFD(RxStateSFD), .StateData(RxStateData),
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| Line 600... |
Line 604... |
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort)
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.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort)
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);
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);
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|
|
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// MII Carrier Sense Synchronization
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// MII Carrier Sense Synchronization
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always @ (posedge mtx_clk_pad_i or posedge r_Rst)
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always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
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begin
|
begin
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if(r_Rst)
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if(wb_rst_i)
|
begin
|
begin
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CarrierSense_Tx1 <= #Tp 1'b0;
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CarrierSense_Tx1 <= #Tp 1'b0;
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CarrierSense_Tx2 <= #Tp 1'b0;
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CarrierSense_Tx2 <= #Tp 1'b0;
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end
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end
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else
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else
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| Line 618... |
Line 622... |
|
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assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
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assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
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// MII Collision Synchronization
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// MII Collision Synchronization
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always @ (posedge mtx_clk_pad_i or posedge r_Rst)
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always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
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begin
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begin
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if(r_Rst)
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if(wb_rst_i)
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begin
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begin
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Collision_Tx1 <= #Tp 1'b0;
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Collision_Tx1 <= #Tp 1'b0;
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Collision_Tx2 <= #Tp 1'b0;
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Collision_Tx2 <= #Tp 1'b0;
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end
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end
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else
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else
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| Line 643... |
Line 647... |
assign Collision = ~r_FullD & Collision_Tx2;
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assign Collision = ~r_FullD & Collision_Tx2;
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|
|
|
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// Carrier sense is synchronized to receive clock.
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// Carrier sense is synchronized to receive clock.
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always @ (posedge mrx_clk_pad_i or posedge r_Rst)
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always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
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begin
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begin
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if(r_Rst)
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if(wb_rst_i)
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begin
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begin
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CarrierSense_Rx1 <= #Tp 1'h0;
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CarrierSense_Rx1 <= #Tp 1'h0;
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RxCarrierSense <= #Tp 1'h0;
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RxCarrierSense <= #Tp 1'h0;
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end
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end
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else
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else
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| Line 671... |
Line 675... |
assign Transmitting = ~r_FullD & WillTransmit_q2;
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assign Transmitting = ~r_FullD & WillTransmit_q2;
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|
|
|
|
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// Synchronized Receive Enable
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// Synchronized Receive Enable
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always @ (posedge mrx_clk_pad_i or posedge r_Rst)
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always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
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begin
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begin
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if(r_Rst)
|
if(wb_rst_i)
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RxEnSync <= #Tp 1'b0;
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RxEnSync <= #Tp 1'b0;
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else
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else
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if(~RxCarrierSense | RxCarrierSense & Transmitting)
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if(~RxCarrierSense | RxCarrierSense & Transmitting)
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RxEnSync <= #Tp r_RxEn;
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RxEnSync <= #Tp r_RxEn;
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end
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end
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| Line 726... |
Line 730... |
|
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
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.BDCs(BDCs), .WB_ACK_O(BDAck),
|
|
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.Reset(r_Rst),
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.Reset(wb_rst_i),
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|
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// WISHBONE master
|
// WISHBONE master
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_adr_o(m_wb_adr_o), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
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.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
|
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
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| Line 778... |
Line 782... |
|
|
|
|
// Connecting MacStatus module
|
// Connecting MacStatus module
|
eth_macstatus macstatus1
|
eth_macstatus macstatus1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .Reset(r_Rst),
|
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
|
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
|
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
|
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
|
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
|
