| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.41 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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// Revision 1.40 2002/11/19 17:34:25 mohor
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// Revision 1.40 2002/11/19 17:34:25 mohor
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
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// that a frame was received because of the promiscous mode.
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// that a frame was received because of the promiscous mode.
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//
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//
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// Revision 1.39 2002/11/18 17:31:55 mohor
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// Revision 1.39 2002/11/18 17:31:55 mohor
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| Line 337... |
Line 340... |
reg WillSendControlFrame_sync1;
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reg WillSendControlFrame_sync1;
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reg WillSendControlFrame_sync2;
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reg WillSendControlFrame_sync2;
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reg WillSendControlFrame_sync3;
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reg WillSendControlFrame_sync3;
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reg RstTxPauseRq;
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reg RstTxPauseRq;
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reg TxPauseRq_sync1;
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reg TxPauseRq_sync2;
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reg TxPauseRq_sync3;
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reg TPauseRq;
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// Connecting Miim module
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// Connecting Miim module
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eth_miim miim1
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eth_miim miim1
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(
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(
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.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
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.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
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| Line 513... |
Line 521... |
wire [1:0] StateData;
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wire [1:0] StateData;
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// Connecting MACControl
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// Connecting MACControl
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eth_maccontrol maccontrol1
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eth_maccontrol maccontrol1
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(
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(
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.MTxClk(mtx_clk_pad_i), .TPauseRq(r_TxPauseRq),
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.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
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.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
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.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
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.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
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.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
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.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
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.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
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.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
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.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
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.RxData(RxData), .RxValid(RxValid),
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.RxData(RxData), .RxValid(RxValid),
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| Line 731... |
Line 739... |
else
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else
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RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
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RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
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end
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end
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// TX Pause request Synchronization
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always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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begin
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TxPauseRq_sync1 <= #Tp 1'b0;
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TxPauseRq_sync2 <= #Tp 1'b0;
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TxPauseRq_sync3 <= #Tp 1'b0;
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end
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else
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begin
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TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
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TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
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TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
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end
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end
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always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
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begin
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if(wb_rst_i)
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TPauseRq <= #Tp 1'b0;
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else
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TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
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end
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// Connecting Wishbone module
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// Connecting Wishbone module
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eth_wishbone wishbone
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eth_wishbone wishbone
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(
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(
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
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.WB_DAT_O(BD_WB_DAT_O),
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.WB_DAT_O(BD_WB_DAT_O),
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