ࡱ> /9.p7 $bjbjUU NJ7|7|o |l ###4D$///h//LD$e.//"00L0t44 4eeeeeee$g iCe#43|t444Ce,6 0L0Xe,6,6,64 &0:#L0e,64e,6,6=Z"#qdL0/ 0Y`D$ /45mcqdne0ecj5vjqd,6#.#J  Ethernet IP Core Introduction The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively. Features Figure 1: Core Architecture Overview The core provides the following features: Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x) Collision detection and auto re-transmission on collisions in half duplex mode (CSMA/CD protocol) Automatic 32-bit CRC generation and checking Preamble generation and removal Complete status for TX/RX packets IEEE 802.3 Media Independent Interface (MII) WISHBONE SoC Interconnection Rev. B compliant interface General Description Architecture Adjoining figure shows the general architecture of the Ethernet IP core. It consists of several building blocks: TX Ethernet MAC (transmit function) block with the CRC generator RX Ethernet MAC (receive function) block with the CRC generator MAC control block Management block (MIIM) Host interface TX and RX Modules The TX and RX modules provide full transmit and receive functionality. CRC generators are incorporated in both modules for error detection purposes. The modules also handle preamble generation and removal. Padding occurs automatically (when enabled) in compliance with the IEEE 802.3 standard. When enabled, packets greater than the standard can be transmitted. Control Module The control module provides full duplex flow control, according to the IEEE 802.3u standard. Flow control is achieved by transfering the PAUSE control frames between the communicating stations. Management Module (MIIM) The management module provides the standard IEEE 802.3 Media Independent Interface (MII) that defines the connection between the PHY and link layers. Using this interface, the device (RISC) connected to the host interface can force PHY to run at 10 Mbps versus 100 Mbps or to configure it to run at full versus half duplex mode. WISHBONE Interface The WISHBONE interface connects the Ethernet core to the RISC and to external memory. The core is WISHBONE SoC Interconnection specification Rev. B compliant. The implementation realizes a 32-bit bus width and does not support other bus widths. Utilization The following table lists the cores intended applications. TechnologyFPGA SizeSilicon AreaSpeedPower ConsumptionXilinx Virtex2600 slices100000 gates60 MHz  (footnote continued) PAGE  PAGE 2 Ethernet IP Core Ethernet IP Core Authors reserve the right to make changes in specifications at any time and without notice. The information in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by the Authors for its use, nor for any infringements of patents or other rights of third parties resulting from its use. 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It consists of a synthesizable 7*)*%J;7%*)   *% ())% %%*%M2 i,Verilog RTL core that provides all features <%*)97429%*%9)%8**)*% 8%8%%)% R2 /necessary to implement the Layer 2 protocol of )%%% %(!*!?*%?%)!)%!2%(%!* ***%* *82 ( the Ethernet standard. It is d)%83)%)%8 %)*%*88 7*"2 ( Fesigned to run e% ))%*7*7))F2 'according to the IEEE 802.3 and 802.3u %%%**))I*I)%I333I****H%)*H****)R2 /specifications that define the 10 Mbps and 100 *%%%%*) #)%#*%)%#)%#**"J** "%)*"***F2 H 'Mbps Ethernet standards, respectively. J** 3)%)% %)*%* % *%%)%( 2 H  % 2  % - !wb - -2 b Features9449#44 2 b  4- - '@Times New RomanLSwUSw0-A2 $Figure 1: Core Architecture Overview.&&!&2&!.!&!!&!6!!!!2 2 `  '-I2 )The core provides the following features:4)%%*%**)*% )%**:))%%)%  2 J %@Symbolw@Y LSwUSw0- 2 ! & 2 !2 p-22 *Flow control and automatic.*:(%*)*(%)*(%)*?%%"2 *m generation of e()%)%%*)(*'I2 )control frames in full duplex mode (IEEE %*)*$%?% $)$)#*)*%)#?**%#333'2 802.3x)s****) 2  %'- 2 F & 2 F2 p-:2 OCollision detection and auto re7* *)*%%%*)%)*~%)*~% 2 OE -'J2 *transmission on collisions in half duplex %) ? *)/*)/%* *) /)/)%.*)*%)'.2 mode (CSMA/CD protocol)?**%7.J;7<***%* 2 G %'- 2 l & 2 l2 p-2 u Automatic 32;)*?%%H** 2 u-.2 ubit CRC generation and *H777H)%)%%*)H%)*'2 checking%)%%))) 2  %'- 2 1 & 2 12 p-:2 :Preamble generation and removal/%%?*%)%)%%*)%)*%?*)% 2 : %'- 2  & 2 2 p-%2 Complete status f7*?*%% %) #2 or TX/RX packets*4<7<*%%)% 2 H %'- 2  & 2 2 p-F2 'IEEE 802.3 Media Independent Interface 333.****-J%*%-)*%*%)*%)-)%%%%'2 f(MII)J 2 f\ %'- 2  & 2   p-A2 @ $WISHBONE SoC Interconnection Rev. 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It consists of several *+)%+3)%)%+/+%*%++%*)   *** %)%%2 S building*)*))2 S  blocks:**%)  2 S  %- 2 & 2  p-A2 @ $TX Ethernet MAC (transmit function) 4<H3)%)%HJ;7H%) ?H))%*)'52 K @ block with the CRC generator**%):))%777)%)%%* 2 K " %'- 2 & 2  p-I2 @ )RX Ethernet MAC (receive function) block 7<3)%)%J;7%%%)%))%*)**%)',2  @ with the CRC generator:))%777)%)%%* 2  T %'- 2 m & 2 m  p-&2 v @ MAC control block J;7%*)***%) 2 v  %'- 2 & 2  p-.2 @ Management block (MIIM)J%)%)%?%)**%)JJ 2  %'- 2 9 & 2 9  p- 2 B @ Host interface<* )%%%% 2 B   %' 2  %@"Arialw@] LSwUSw0- %2  TX and RX Modules 37.33<7C333.. 2   .-G2 a (The TX and RX modules provide full trans4)%%4<%%)*$7<$?**)% $**)*%$)$%) 2 amit ?P2  .and receive functionality. CRC generators are %)*/%%%)%/))%*)%(/777/)%)%%* /%%U2 ! 1incorporated in both modules for error detection )%***%%*)**)?**)% *%**%%%*)L2  +purposes. The modules also handle preamble *)** % 44)%4?**)% 4% *4)%)*%3*%%?*%F2  'generation and removal. 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