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[/] [ethmac/] [trunk/] [README.txt] - Diff between revs 338 and 347
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// README.txt ////
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//// README.txt ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/project,ethmac ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Olof Kindgren (olof@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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RUNNING the simulation/Testbench in Icarus Verilog:
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Go to the scripts directory and write "make rtl-tests"
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All logs will be saved in the log directory
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VCD dumps are coming soon
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RUNNING the simulation/Testbench in ModelSIM:
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RUNNING the simulation/Testbench in ModelSIM:
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Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
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Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
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Run the macro do.do (write "do do.do" in the command window).
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Run the macro do.do (write "do do.do" in the command window).
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Simulation will be automatically started. Logs are stored in the /log
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Simulation will be automatically started. Logs are stored in the /log
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