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////  README.txt                                                  ////
////  README.txt                                                  ////
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////  This file is part of the Ethernet IP core project           ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////  http://www.opencores.org/project,ethmac                     ////
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////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Igor Mohor (igorM@opencores.org)                      ////
 
////      - Olof Kindgren (olof@opencores.org)                    ////
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//// Copyright (C) 2001, 2002 Authors                             ////
//// Copyright (C) 2001, 2002 Authors                             ////
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RUNNING the simulation/Testbench in Icarus Verilog:
 
 
 
Go to the scripts directory and write "make rtl-tests"
 
All logs will be saved in the log directory
 
 
 
VCD dumps are coming soon
 
 
RUNNING the simulation/Testbench in ModelSIM:
RUNNING the simulation/Testbench in ModelSIM:
 
 
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
Run the macro do.do (write "do do.do" in the command window).
Run the macro do.do (write "do do.do" in the command window).
Simulation will be automatically started. Logs are stored in the /log
Simulation will be automatically started. Logs are stored in the /log

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