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[/] [ethmac/] [trunk/] [bench/] [verilog/] [eth_phy.v] - Diff between revs 188 and 191
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| Rev 188 |
Rev 191 |
| Line 419... |
Line 419... |
begin
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begin
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#4 ;
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#4 ;
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`ifdef VERBOSE
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`ifdef VERBOSE
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$fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time);
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$fdisplay(phy_log, " (%0t)(%m)MIIM - 32-bit preamble received", $time);
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`endif
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`endif
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if (md_io_reg !== 1'b0)
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// check start bit only if md_transfer_cnt_reset is inactive, because if
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// preamble suppression was changed start bit should not be checked
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if ((md_io_reg !== 1'b0) && (md_transfer_cnt_reset == 1'b0))
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begin
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begin
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// ERROR - start !
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// ERROR - start !
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`ifdef VERBOSE
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`ifdef VERBOSE
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$fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time);
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$fdisplay(phy_log, "*E (%0t)(%m)MIIM - wrong first start bit", $time);
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`endif
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`endif
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