| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/09/18 17:55:08 tadej
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// Bug repaired in eth_phy device
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//
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// Revision 1.3 2002/09/13 14:50:15 mohor
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// Revision 1.3 2002/09/13 14:50:15 mohor
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// Bug in MIIM fixed.
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// Bug in MIIM fixed.
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//
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//
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Revision 1.2 2002/09/13 12:29:14 mohor
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// Headers changed.
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// Headers changed.
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| Line 1121... |
Line 1124... |
mrxerr_o = 0;
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mrxerr_o = 0;
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mcrs_rx = 0;
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mcrs_rx = 0;
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end
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end
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task send_rx_packet;
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task send_rx_packet;
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input [(8*32)-1:0] preamble_data; // preamble data to be sent
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input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
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input [3:0] preamble_len; // length of preamble - max is 8
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input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
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input [7:0] sfd_data; // SFD data to be sent
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input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
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input [31:0] start_addr; // start address
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input [31:0] start_addr; // start address
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input [31:0] len; // length of frame in Bytes (without preamble and SFD)
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input [31:0] len; // length of frame in Bytes (without preamble and SFD)
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input plus_drible_nibble; // if length is longer for one nibble
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input plus_drible_nibble; // if length is longer for one nibble
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integer rx_cnt;
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integer rx_cnt;
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reg [31:0] rx_mem_addr_in; // address for reading from RX memory
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reg [31:0] rx_mem_addr_in; // address for reading from RX memory
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Line 1150... |
`endif
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`endif
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// set initial rx memory address
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// set initial rx memory address
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rx_mem_addr_in = start_addr;
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rx_mem_addr_in = start_addr;
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// send preamble
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// send preamble
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for (rx_cnt = 0; (rx_cnt < preamble_len) || (rx_cnt < 8); rx_cnt = rx_cnt + 1)
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for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
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begin
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begin
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#1 mrxd_o = preamble_data[3:0];
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#1 mrxd_o = preamble_data[3:0];
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#1 preamble_data = preamble_data >> 4;
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#1 preamble_data = preamble_data >> 4;
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@(posedge mrx_clk_o);
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@(posedge mrx_clk_o);
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end
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end
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| Line 1167... |
Line 1170... |
$fdisplay(phy_log, " (%0t)(%m) RX frame preamble and SFD sent!", $time);
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$fdisplay(phy_log, " (%0t)(%m) RX frame preamble and SFD sent!", $time);
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`endif
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`endif
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// send packet's addresses, type/length, data and FCS
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// send packet's addresses, type/length, data and FCS
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for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
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for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
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begin
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begin
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@(posedge mrx_clk_o);
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#1;
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#1;
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rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
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rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
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mrxd_o = rx_mem_data_out[3:0];
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mrxd_o = rx_mem_data_out[3:0];
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@(posedge mrx_clk_o);
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@(posedge mrx_clk_o);
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#1;
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#1;
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mrxd_o = rx_mem_data_out[7:4];
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mrxd_o = rx_mem_data_out[7:4];
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rx_mem_addr_in = rx_mem_addr_in + 1;
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rx_mem_addr_in = rx_mem_addr_in + 1;
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@(posedge mrx_clk_o);
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#1;
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#1;
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end
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end
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if (plus_drible_nibble)
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if (plus_drible_nibble)
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begin
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begin
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@(posedge mrx_clk_o);
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#1;
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rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
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rx_mem_data_out = rx_mem[rx_mem_addr_in[21:0]];
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mrxd_o = rx_mem_data_out[3:0];
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mrxd_o = rx_mem_data_out[3:0];
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@(posedge mrx_clk_o);
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end
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end
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`ifdef VERBOSE
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`ifdef VERBOSE
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$fdisplay(phy_log, " (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
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$fdisplay(phy_log, " (%0t)(%m) RX frame addresses, type/length, data and FCS sent!", $time);
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`endif
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`endif
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@(posedge mrx_clk_o);
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#1 mcrs_rx = 0;
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#1 mcrs_rx = 0;
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#1 mrxdv_o = 0;
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#1 mrxdv_o = 0;
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@(posedge mrx_clk_o);
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`ifdef VERBOSE
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`ifdef VERBOSE
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$fdisplay(phy_log, " (%0t)(%m) RX frame ended with rx_dv reset!", $time);
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$fdisplay(phy_log, " (%0t)(%m) RX frame ended with rx_dv reset!", $time);
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`endif
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`endif
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end
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end
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endtask // send_rx_packet
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endtask // send_rx_packet
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