| Line 39... |
Line 39... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2002/11/19 20:27:46 mohor
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// Temp version.
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//
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// Revision 1.9 2002/10/09 13:16:51 tadejm
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// Revision 1.9 2002/10/09 13:16:51 tadejm
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// Just back-up; not completed testbench and some testcases are not
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// Just back-up; not completed testbench and some testcases are not
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// wotking properly yet.
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// wotking properly yet.
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//
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//
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// Revision 1.8 2002/09/13 18:41:45 mohor
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// Revision 1.8 2002/09/13 18:41:45 mohor
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`define TX_BUF_BASE `MEMORY_BASE
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`define TX_BUF_BASE `MEMORY_BASE
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`define RX_BUF_BASE `MEMORY_BASE + 32'h8000
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`define RX_BUF_BASE `MEMORY_BASE + 32'h8000
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`define TX_BD_BASE `ETH_BASE + 32'h00000400
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`define TX_BD_BASE `ETH_BASE + 32'h00000400
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`define RX_BD_BASE `ETH_BASE + 32'h00000600
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`define RX_BD_BASE `ETH_BASE + 32'h00000600
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`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
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`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
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`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
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`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
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/* Tx BD */
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/* Tx BD */
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`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
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`define ETH_TX_BD_READY 32'h8000 /* Tx BD Ready */
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`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
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`define ETH_TX_BD_IRQ 32'h4000 /* Tx BD IRQ Enable */
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`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */
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`define ETH_TX_BD_WRAP 32'h2000 /* Tx BD Wrap (last BD) */
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`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */
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`define ETH_TX_BD_PAD 32'h1000 /* Tx BD Pad Enable */
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